phase_shift_sin.fit.qmsg

来自「实现低频率的移相信号发生器,才用DDS技术直接的合成」· QMSG 代码 · 共 51 行 · 第 1/5 页

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.353 ns register register " "Info: Estimated most critical path is register to register delay of 4.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\] 1 REG LAB_X20_Y9 50 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X20_Y9; Fanout = 50; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.862 ns) + CELL(0.590 ns) 1.452 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~13 2 COMB LAB_X20_Y8 1 " "Info: 2: + IC(0.862 ns) + CELL(0.590 ns) = 1.452 ns; Loc. = LAB_X20_Y8; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~13'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "1.452 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 } "NODE_NAME" } "" } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1020 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.084 ns) + CELL(0.292 ns) 2.828 ns sld_hub:sld_hub_inst\|hub_tdo~1105 3 COMB LAB_X20_Y9 1 " "Info: 3: + IC(1.084 ns) + CELL(0.292 ns) = 2.828 ns; Loc. = LAB_X20_Y9; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~1105'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "1.376 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~1105 } "NODE_NAME" } "" } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.075 ns) + CELL(0.590 ns) 3.493 ns sld_hub:sld_hub_inst\|hub_tdo~1107 4 COMB LAB_X20_Y9 1 " "Info: 4: + IC(0.075 ns) + CELL(0.590 ns) = 3.493 ns; Loc. = LAB_X20_Y9; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~1107'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "0.665 ns" { sld_hub:sld_hub_inst|hub_tdo~1105 sld_hub:sld_hub_inst|hub_tdo~1107 } "NODE_NAME" } "" } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.551 ns) + CELL(0.309 ns) 4.353 ns sld_hub:sld_hub_inst\|hub_tdo 5 REG LAB_X20_Y9 1 " "Info: 5: + IC(0.551 ns) + CELL(0.309 ns) = 4.353 ns; Loc. = LAB_X20_Y9; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "0.860 ns" { sld_hub:sld_hub_inst|hub_tdo~1107 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.781 ns ( 40.91 % ) " "Info: Total cell delay = 1.781 ns ( 40.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.572 ns ( 59.09 % ) " "Info: Total interconnect delay = 2.572 ns ( 59.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "4.353 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~1105 sld_hub:sld_hub_inst|hub_tdo~1107 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 8 " "Info: Average interconnect usage is 5% of the available device resources. Peak interconnect usage is 8%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}