phase_shift_sin.fit.qmsg

来自「实现低频率的移相信号发生器,才用DDS技术直接的合成」· QMSG 代码 · 共 51 行 · 第 1/5 页

{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~TCKUTAP\" to use Global clock" {  } { { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock " "Info: Automatically promoted signal \"clk\" to use Global clock" {  } { { "phase_shift_sin.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 6 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "clk " "Info: Pin \"clk\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "phase_shift_sin.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 6 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { clk } "NODE_NAME" } "" } } { "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" { Floorplan "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.fld" "" "" { clk } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_signaltap:auto_signaltap_0\|reset_all Global clock " "Info: Automatically promoted some destinations of signal \"sld_signaltap:auto_signaltap_0\|reset_all\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " "Info: Destination \"sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset\" may be non-global or may not use global clock" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" 415 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "d:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" 415 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|CLRN_SIGNAL Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|CLRN_SIGNAL\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_signaltap:auto_signaltap_0\|reset_all " "Info: Destination \"sld_signaltap:auto_signaltap_0\|reset_all\" may be non-global or may not use global clock" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_signaltap.vhd" 415 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 307 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" may be non-global or may not use global clock" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\]\" may be non-global or may not use global clock" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~1099 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~1099\" may be non-global or may not use global clock" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~1100 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~1100\" may be non-global or may not use global clock" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg " "Info: Destination \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg\" may be non-global or may not use global clock" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 708 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 " "Info: Destination \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "d:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:2:IRF\|Q\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~1102 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~1102\" may be non-global or may not use global clock" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~1103 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~1103\" may be non-global or may not use global clock" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sin_rom:u4\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg " "Info: Destination \"sin_rom:u4\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg\" may be non-global or may not use global clock" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_mod_ram_rom.vhd" 708 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sin_rom:u4\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 " "Info: Destination \"sin_rom:u4\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "d:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset Global clock " "Info: Automatically promoted signal \"sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset\" to use Global clock" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" 415 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}