phase_shift_sin.hier_info

来自「实现低频率的移相信号发生器,才用DDS技术直接的合成」· HIER_INFO 代码 · 共 1,642 行 · 第 1/5 页

cin[3] => cout[3]~4.IN0
cin[4] => cout[4]~3.IN0
cin[5] => cout[5]~2.IN0
cin[6] => cout[6]~1.IN0
cin[7] => cout[7]~0.IN0
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
sout[0] <= sout_node[0].DB_MAX_OUTPUT_PORT_TYPE
sout[1] <= sout_node[1].DB_MAX_OUTPUT_PORT_TYPE
sout[2] <= sout_node[2].DB_MAX_OUTPUT_PORT_TYPE
sout[3] <= sout_node[3].DB_MAX_OUTPUT_PORT_TYPE
sout[4] <= sout_node[4].DB_MAX_OUTPUT_PORT_TYPE
sout[5] <= sout_node[5].DB_MAX_OUTPUT_PORT_TYPE
sout[6] <= sout_node[6].DB_MAX_OUTPUT_PORT_TYPE
sout[7] <= sout_node[7].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cout[0]~7.DB_MAX_OUTPUT_PORT_TYPE
cout[1] <= cout[1]~6.DB_MAX_OUTPUT_PORT_TYPE
cout[2] <= cout[2]~5.DB_MAX_OUTPUT_PORT_TYPE
cout[3] <= cout[3]~4.DB_MAX_OUTPUT_PORT_TYPE
cout[4] <= cout[4]~3.DB_MAX_OUTPUT_PORT_TYPE
cout[5] <= cout[5]~2.DB_MAX_OUTPUT_PORT_TYPE
cout[6] <= cout[6]~1.DB_MAX_OUTPUT_PORT_TYPE
cout[7] <= cout[7]~0.DB_MAX_OUTPUT_PORT_TYPE


|phase_shift_sin|adder8:u2|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:result_node
sin[0] => cs_buffer[0].SUM_IN
sin[1] => cs_buffer[1].SUM_IN
sin[2] => cs_buffer[2].SUM_IN
sin[3] => cs_buffer[3].SUM_IN
sin[4] => cs_buffer[4].SUM_IN
sin[5] => cs_buffer[5].SUM_IN
sin[6] => cs_buffer[6].SUM_IN
sin[7] => cs_buffer[7].SUM_IN
cin[0] => cs_buffer[0].CIN
cin[1] => cs_buffer[1].CIN
cin[2] => cs_buffer[2].CIN
cin[3] => cs_buffer[3].CIN
cin[4] => cs_buffer[4].CIN
cin[5] => cs_buffer[5].CIN
cin[6] => cs_buffer[6].CIN
cin[7] => cs_buffer[7].CIN
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
sout[0] <= cs_buffer[0].DB_MAX_OUTPUT_PORT_TYPE
sout[1] <= cs_buffer[1].DB_MAX_OUTPUT_PORT_TYPE
sout[2] <= cs_buffer[2].DB_MAX_OUTPUT_PORT_TYPE
sout[3] <= cs_buffer[3].DB_MAX_OUTPUT_PORT_TYPE
sout[4] <= cs_buffer[4].DB_MAX_OUTPUT_PORT_TYPE
sout[5] <= cs_buffer[5].DB_MAX_OUTPUT_PORT_TYPE
sout[6] <= cs_buffer[6].DB_MAX_OUTPUT_PORT_TYPE
sout[7] <= cs_buffer[7].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cs_buffer[0].DB_MAX_OUTPUT_PORT_TYPE
cout[1] <= cs_buffer[1].DB_MAX_OUTPUT_PORT_TYPE
cout[2] <= cs_buffer[2].DB_MAX_OUTPUT_PORT_TYPE
cout[3] <= cs_buffer[3].DB_MAX_OUTPUT_PORT_TYPE
cout[4] <= cs_buffer[4].DB_MAX_OUTPUT_PORT_TYPE
cout[5] <= cs_buffer[5].DB_MAX_OUTPUT_PORT_TYPE
cout[6] <= cs_buffer[6].DB_MAX_OUTPUT_PORT_TYPE
cout[7] <= cs_buffer[7].DB_MAX_OUTPUT_PORT_TYPE


|phase_shift_sin|adder8:u2|lpm_add_sub:lpm_add_sub_component|addcore:adder|a_csnbuffer:cout_node
sin[0] => sout_node[0].DATAIN
sin[1] => sout_node[1].DATAIN
sin[2] => sout_node[2].DATAIN
sin[3] => sout_node[3].DATAIN
sin[4] => sout_node[4].DATAIN
sin[5] => sout_node[5].DATAIN
sin[6] => sout_node[6].DATAIN
sin[7] => sout_node[7].DATAIN
cin[0] => cout[0]~7.IN0
cin[1] => cout[1]~6.IN0
cin[2] => cout[2]~5.IN0
cin[3] => cout[3]~4.IN0
cin[4] => cout[4]~3.IN0
cin[5] => cout[5]~2.IN0
cin[6] => cout[6]~1.IN0
cin[7] => cout[7]~0.IN0
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
sout[0] <= sout_node[0].DB_MAX_OUTPUT_PORT_TYPE
sout[1] <= sout_node[1].DB_MAX_OUTPUT_PORT_TYPE
sout[2] <= sout_node[2].DB_MAX_OUTPUT_PORT_TYPE
sout[3] <= sout_node[3].DB_MAX_OUTPUT_PORT_TYPE
sout[4] <= sout_node[4].DB_MAX_OUTPUT_PORT_TYPE
sout[5] <= sout_node[5].DB_MAX_OUTPUT_PORT_TYPE
sout[6] <= sout_node[6].DB_MAX_OUTPUT_PORT_TYPE
sout[7] <= sout_node[7].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cout[0]~7.DB_MAX_OUTPUT_PORT_TYPE
cout[1] <= cout[1]~6.DB_MAX_OUTPUT_PORT_TYPE
cout[2] <= cout[2]~5.DB_MAX_OUTPUT_PORT_TYPE
cout[3] <= cout[3]~4.DB_MAX_OUTPUT_PORT_TYPE
cout[4] <= cout[4]~3.DB_MAX_OUTPUT_PORT_TYPE
cout[5] <= cout[5]~2.DB_MAX_OUTPUT_PORT_TYPE
cout[6] <= cout[6]~1.DB_MAX_OUTPUT_PORT_TYPE
cout[7] <= cout[7]~0.DB_MAX_OUTPUT_PORT_TYPE


|phase_shift_sin|adder8:u2|lpm_add_sub:lpm_add_sub_component|altshift:result_ext_latency_ffs
data[0] => result[0].DATAIN
data[1] => result[1].DATAIN
data[2] => result[2].DATAIN
data[3] => result[3].DATAIN
data[4] => result[4].DATAIN
data[5] => result[5].DATAIN
data[6] => result[6].DATAIN
data[7] => result[7].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= data[7].DB_MAX_OUTPUT_PORT_TYPE


|phase_shift_sin|adder8:u2|lpm_add_sub:lpm_add_sub_component|altshift:carry_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|phase_shift_sin|adder8:u2|lpm_add_sub:lpm_add_sub_component|altshift:oflow_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|phase_shift_sin|sin_rom:u3
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]


|phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_66u:auto_generated.address_a[0]
address_a[1] => altsyncram_66u:auto_generated.address_a[1]
address_a[2] => altsyncram_66u:auto_generated.address_a[2]
address_a[3] => altsyncram_66u:auto_generated.address_a[3]
address_a[4] => altsyncram_66u:auto_generated.address_a[4]
address_a[5] => altsyncram_66u:auto_generated.address_a[5]
address_a[6] => altsyncram_66u:auto_generated.address_a[6]
address_a[7] => altsyncram_66u:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_66u:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_66u:auto_generated.q_a[0]
q_a[1] <= altsyncram_66u:auto_generated.q_a[1]
q_a[2] <= altsyncram_66u:auto_generated.q_a[2]
q_a[3] <= altsyncram_66u:auto_generated.q_a[3]
q_a[4] <= altsyncram_66u:auto_generated.q_a[4]
q_a[5] <= altsyncram_66u:auto_generated.q_a[5]
q_a[6] <= altsyncram_66u:auto_generated.q_a[6]
q_a[7] <= altsyncram_66u:auto_generated.q_a[7]
q_b[0] <= <GND>


|phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated
address_a[0] => altsyncram_4r92:altsyncram1.address_a[0]
address_a[1] => altsyncram_4r92:altsyncram1.address_a[1]
address_a[2] => altsyncram_4r92:altsyncram1.address_a[2]
address_a[3] => altsyncram_4r92:altsyncram1.address_a[3]
address_a[4] => altsyncram_4r92:altsyncram1.address_a[4]
address_a[5] => altsyncram_4r92:altsyncram1.address_a[5]
address_a[6] => altsyncram_4r92:altsyncram1.address_a[6]
address_a[7] => altsyncram_4r92:altsyncram1.address_a[7]
clock0 => altsyncram_4r92:altsyncram1.clock0
q_a[0] <= altsyncram_4r92:altsyncram1.q_a[0]
q_a[1] <= altsyncram_4r92:altsyncram1.q_a[1]
q_a[2] <= altsyncram_4r92:altsyncram1.q_a[2]
q_a[3] <= altsyncram_4r92:altsyncram1.q_a[3]
q_a[4] <= altsyncram_4r92:altsyncram1.q_a[4]
q_a[5] <= altsyncram_4r92:altsyncram1.q_a[5]
q_a[6] <= altsyncram_4r92:altsyncram1.q_a[6]
q_a[7] <= altsyncram_4r92:altsyncram1.q_a[7]


|phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1
address_a[0] => ram_block3a0.PORTAADDR
address_a[0] => ram_block3a1.PORTAADDR
address_a[0] => ram_block3a2.PORTAADDR
address_a[0] => ram_block3a3.PORTAADDR
address_a[0] => ram_block3a4.PORTAADDR
address_a[0] => ram_block3a5.PORTAADDR
address_a[0] => ram_block3a6.PORTAADDR
address_a[0] => ram_block3a7.PORTAADDR
address_a[1] => ram_block3a0.PORTAADDR1
address_a[1] => ram_block3a1.PORTAADDR1
address_a[1] => ram_block3a2.PORTAADDR1
address_a[1] => ram_block3a3.PORTAADDR1
address_a[1] => ram_block3a4.PORTAADDR1
address_a[1] => ram_block3a5.PORTAADDR1
address_a[1] => ram_block3a6.PORTAADDR1
address_a[1] => ram_block3a7.PORTAADDR1
address_a[2] => ram_block3a0.PORTAADDR2
address_a[2] => ram_block3a1.PORTAADDR2
address_a[2] => ram_block3a2.PORTAADDR2
address_a[2] => ram_block3a3.PORTAADDR2
address_a[2] => ram_block3a4.PORTAADDR2
address_a[2] => ram_block3a5.PORTAADDR2
address_a[2] => ram_block3a6.PORTAADDR2
address_a[2] => ram_block3a7.PORTAADDR2
address_a[3] => ram_block3a0.PORTAADDR3
address_a[3] => ram_block3a1.PORTAADDR3
address_a[3] => ram_block3a2.PORTAADDR3
address_a[3] => ram_block3a3.PORTAADDR3
address_a[3] => ram_block3a4.PORTAADDR3
address_a[3] => ram_block3a5.PORTAADDR3
address_a[3] => ram_block3a6.PORTAADDR3
address_a[3] => ram_block3a7.PORTAADDR3
address_a[4] => ram_block3a0.PORTAADDR4
address_a[4] => ram_block3a1.PORTAADDR4
address_a[4] => ram_block3a2.PORTAADDR4
address_a[4] => ram_block3a3.PORTAADDR4
address_a[4] => ram_block3a4.PORTAADDR4
address_a[4] => ram_block3a5.PORTAADDR4
address_a[4] => ram_block3a6.PORTAADDR4
address_a[4] => ram_block3a7.PORTAADDR4
address_a[5] => ram_block3a0.PORTAADDR5
address_a[5] => ram_block3a1.PORTAADDR5
address_a[5] => ram_block3a2.PORTAADDR5
address_a[5] => ram_block3a3.PORTAADDR5
address_a[5] => ram_block3a4.PORTAADDR5
address_a[5] => ram_block3a5.PORTAADDR5
address_a[5] => ram_block3a6.PORTAADDR5
address_a[5] => ram_block3a7.PORTAADDR5
address_a[6] => ram_block3a0.PORTAADDR6
address_a[6] => ram_block3a1.PORTAADDR6
address_a[6] => ram_block3a2.PORTAADDR6
address_a[6] => ram_block3a3.PORTAADDR6
address_a[6] => ram_block3a4.PORTAADDR6
address_a[6] => ram_block3a5.PORTAADDR6
address_a[6] => ram_block3a6.PORTAADDR6
address_a[6] => ram_block3a7.PORTAADDR6
address_a[7] => ram_block3a0.PORTAADDR7
address_a[7] => ram_block3a1.PORTAADDR7
address_a[7] => ram_block3a2.PORTAADDR7
address_a[7] => ram_block3a3.PORTAADDR7
address_a[7] => ram_block3a4.PORTAADDR7
address_a[7] => ram_block3a5.PORTAADDR7
address_a[7] => ram_block3a6.PORTAADDR7
address_a[7] => ram_block3a7.PORTAADDR7
address_b[0] => ram_block3a0.PORTBADDR
address_b[0] => ram_block3a1.PORTBADDR
address_b[0] => ram_block3a2.PORTBADDR
address_b[0] => ram_block3a3.PORTBADDR
address_b[0] => ram_block3a4.PORTBADDR
address_b[0] => ram_block3a5.PORTBADDR
address_b[0] => ram_block3a6.PORTBADDR
address_b[0] => ram_block3a7.PORTBADDR
address_b[1] => ram_block3a0.PORTBADDR1
address_b[1] => ram_block3a1.PORTBADDR1
address_b[1] => ram_block3a2.PORTBADDR1
address_b[1] => ram_block3a3.PORTBADDR1
address_b[1] => ram_block3a4.PORTBADDR1
address_b[1] => ram_block3a5.PORTBADDR1
address_b[1] => ram_block3a6.PORTBADDR1
address_b[1] => ram_block3a7.PORTBADDR1
address_b[2] => ram_block3a0.PORTBADDR2
address_b[2] => ram_block3a1.PORTBADDR2
address_b[2] => ram_block3a2.PORTBADDR2
address_b[2] => ram_block3a3.PORTBADDR2
address_b[2] => ram_block3a4.PORTBADDR2
address_b[2] => ram_block3a5.PORTBADDR2
address_b[2] => ram_block3a6.PORTBADDR2
address_b[2] => ram_block3a7.PORTBADDR2
address_b[3] => ram_block3a0.PORTBADDR3
address_b[3] => ram_block3a1.PORTBADDR3
address_b[3] => ram_block3a2.PORTBADDR3
address_b[3] => ram_block3a3.PORTBADDR3
address_b[3] => ram_block3a4.PORTBADDR3
address_b[3] => ram_block3a5.PORTBADDR3
address_b[3] => ram_block3a6.PORTBADDR3
address_b[3] => ram_block3a7.PORTBADDR3
address_b[4] => ram_block3a0.PORTBADDR4
address_b[4] => ram_block3a1.PORTBADDR4
address_b[4] => ram_block3a2.PORTBADDR4
address_b[4] => ram_block3a3.PORTBADDR4
address_b[4] => ram_block3a4.PORTBADDR4
address_b[4] => ram_block3a5.PORTBADDR4
address_b[4] => ram_block3a6.PORTBADDR4
address_b[4] => ram_block3a7.PORTBADDR4
address_b[5] => ram_block3a0.PORTBADDR5