phase_shift_sin.tan.qmsg

来自「实现低频率的移相信号发生器,才用DDS技术直接的合成」· QMSG 代码 · 共 8 行 · 第 1/5 页

{ "Info" "ITDB_TSU_RESULT" "fword2\[31\] fword\[1\] clk 2.565 ns register " "Info: tsu for register \"fword2\[31\]\" (data pin = \"fword\[1\]\", clock pin = \"clk\") is 2.565 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.008 ns + Longest pin register " "Info: + Longest pin to register delay is 10.008 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fword\[1\] 1 PIN PIN_2 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 4; PIN Node = 'fword\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { fword[1] } "NODE_NAME" } "" } } { "phase_shift_sin.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.491 ns) + CELL(0.575 ns) 8.535 ns fword2\[21\]~125COUT1_133 2 COMB LC_X12_Y9_N5 2 " "Info: 2: + IC(6.491 ns) + CELL(0.575 ns) = 8.535 ns; Loc. = LC_X12_Y9_N5; Fanout = 2; COMB Node = 'fword2\[21\]~125COUT1_133'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "7.066 ns" { fword[1] fword2[21]~125COUT1_133 } "NODE_NAME" } "" } } { "phase_shift_sin.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 8.615 ns fword2\[22\]~121COUT1_134 3 COMB LC_X12_Y9_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 8.615 ns; Loc. = LC_X12_Y9_N6; Fanout = 2; COMB Node = 'fword2\[22\]~121COUT1_134'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "0.080 ns" { fword2[21]~125COUT1_133 fword2[22]~121COUT1_134 } "NODE_NAME" } "" } } { "phase_shift_sin.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 8.695 ns fword2\[23\]~117COUT1_135 4 COMB LC_X12_Y9_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 8.695 ns; Loc. = LC_X12_Y9_N7; Fanout = 2; COMB Node = 'fword2\[23\]~117COUT1_135'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "0.080 ns" { fword2[22]~121COUT1_134 fword2[23]~117COUT1_135 } "NODE_NAME" } "" } } { "phase_shift_sin.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 8.775 ns fword2\[24\]~85COUT1_136 5 COMB LC_X12_Y9_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 8.775 ns; Loc. = LC_X12_Y9_N8; Fanout = 2; COMB Node = 'fword2\[24\]~85COUT1_136'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "0.080 ns" { fword2[23]~117COUT1_135 fword2[24]~85COUT1_136 } "NODE_NAME" } "" } } { "phase_shift_sin.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 9.033 ns fword2\[25\]~89 6 COMB LC_X12_Y9_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 9.033 ns; Loc. = LC_X12_Y9_N9; Fanout = 6; COMB Node = 'fword2\[25\]~89'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "0.258 ns" { fword2[24]~85COUT1_136 fword2[25]~89 } "NODE_NAME" } "" } } { "phase_shift_sin.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 9.169 ns fword2\[30\]~109 7 COMB LC_X12_Y8_N4 1 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 9.169 ns; Loc. = LC_X12_Y8_N4; Fanout = 1; COMB Node = 'fword2\[30\]~109'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "0.136 ns" { fword2[25]~89 fword2[30]~109 } "NODE_NAME" } "" } } { "phase_shift_sin.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 10.008 ns fword2\[31\] 8 REG LC_X12_Y8_N5 3 " "Info: 8: + IC(0.000 ns) + CELL(0.839 ns) = 10.008 ns; Loc. = LC_X12_Y8_N5; Fanout = 3; REG Node = 'fword2\[31\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "0.839 ns" { fword2[30]~109 fword2[31] } "NODE_NAME" } "" } } { "phase_shift_sin.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.517 ns ( 35.14 % ) " "Info: Total cell delay = 3.517 ns ( 35.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.491 ns ( 64.86 % ) " "Info: Total interconnect delay = 6.491 ns ( 64.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "10.008 ns" { fword[1] fword2[21]~125COUT1_133 fword2[22]~121COUT1_134 fword2[23]~117COUT1_135 fword2[24]~85COUT1_136 fword2[25]~89 fword2[30]~109 fword2[31] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.008 ns" { fword[1] fword[1]~out0 fword2[21]~125COUT1_133 fword2[22]~121COUT1_134 fword2[23]~117COUT1_135 fword2[24]~85COUT1_136 fword2[25]~89 fword2[30]~109 fword2[31] } { 0.000ns 0.000ns 6.491ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.575ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "phase_shift_sin.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.480 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.480 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_123 292 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 292; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { clk } "NODE_NAME" } "" } } { "phase_shift_sin.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.294 ns) + CELL(0.711 ns) 7.480 ns fword2\[31\] 2 REG LC_X12_Y8_N5 3 " "Info: 2: + IC(5.294 ns) + CELL(0.711 ns) = 7.480 ns; Loc. = LC_X12_Y8_N5; Fanout = 3; REG Node = 'fword2\[31\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "6.005 ns" { clk fword2[31] } "NODE_NAME" } "" } } { "phase_shift_sin.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 29.22 % ) " "Info: Total cell delay = 2.186 ns ( 29.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.294 ns ( 70.78 % ) " "Info: Total interconnect delay = 5.294 ns ( 70.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "7.480 ns" { clk fword2[31] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.480 ns" { clk clk~out0 fword2[31] } { 0.000ns 0.000ns 5.294ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "10.008 ns" { fword[1] fword2[21]~125COUT1_133 fword2[22]~121COUT1_134 fword2[23]~117COUT1_135 fword2[24]~85COUT1_136 fword2[25]~89 fword2[30]~109 fword2[31] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.008 ns" { fword[1] fword[1]~out0 fword2[21]~125COUT1_133 fword2[22]~121COUT1_134 fword2[23]~117COUT1_135 fword2[24]~85COUT1_136 fword2[25]~89 fword2[30]~109 fword2[31] } { 0.000ns 0.000ns 6.491ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.575ns 0.080ns 0.080ns 0.080ns 0.258ns 0.136ns 0.839ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "7.480 ns" { clk fword2[31] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.480 ns" { clk clk~out0 fword2[31] } { 0.000ns 0.000ns 5.294ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk fout\[5\] sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|altsyncram_4r92:altsyncram1\|q_a\[5\] 13.840 ns memory " "Info: tco from clock \"clk\" to destination pin \"fout\[5\]\" through memory \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_66u:auto_generated\|altsyncram_4r92:altsyncram1\|q_a\[5\]\" is 13.840 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.520 ns + Longest memor