phase_shift_sin.tan.qmsg

来自「实现低频率的移相信号发生器,才用DDS技术直接的合成」· QMSG 代码 · 共 8 行 · 第 1/5 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|safe_q\[1\] register sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|safe_q\[3\] 147.56 MHz 6.777 ns Internal " "Info: Clock \"clk\" has Internal fmax of 147.56 MHz between source register \"sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|safe_q\[1\]\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|safe_q\[3\]\" (period= 6.777 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.516 ns + Longest register register " "Info: + Longest register to register delay is 6.516 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|safe_q\[1\] 1 REG LC_X17_Y4_N1 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y4_N1; Fanout = 6; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|safe_q\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_afd.tdf" "" { Text "E:/老项目/数字移相信号发生器/fpga/db/cntr_afd.tdf" 99 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.564 ns) 1.093 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|counter_cella1~COUT 2 COMB LC_X17_Y4_N1 2 " "Info: 2: + IC(0.529 ns) + CELL(0.564 ns) = 1.093 ns; Loc. = LC_X17_Y4_N1; Fanout = 2; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|counter_cella1~COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "1.093 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[1] sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella1~COUT } "NODE_NAME" } "" } } { "db/cntr_afd.tdf" "" { Text "E:/老项目/数字移相信号发生器/fpga/db/cntr_afd.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.171 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|counter_cella2~COUT 3 COMB LC_X17_Y4_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.171 ns; Loc. = LC_X17_Y4_N2; Fanout = 2; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|counter_cella2~COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "0.078 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella1~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella2~COUT } "NODE_NAME" } "" } } { "db/cntr_afd.tdf" "" { Text "E:/老项目/数字移相信号发生器/fpga/db/cntr_afd.tdf" 49 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.249 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|counter_cella3~COUT 4 COMB LC_X17_Y4_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.249 ns; Loc. = LC_X17_Y4_N3; Fanout = 2; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|counter_cella3~COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "0.078 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella2~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella3~COUT } "NODE_NAME" } "" } } { "db/cntr_afd.tdf" "" { Text "E:/老项目/数字移相信号发生器/fpga/db/cntr_afd.tdf" 57 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.427 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|counter_cella4~COUT 5 COMB LC_X17_Y4_N4 3 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.427 ns; Loc. = LC_X17_Y4_N4; Fanout = 3; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|counter_cella4~COUT'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "0.178 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella3~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella4~COUT } "NODE_NAME" } "" } } { "db/cntr_afd.tdf" "" { Text "E:/老项目/数字移相信号发生器/fpga/db/cntr_afd.tdf" 65 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.048 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|cout 6 COMB LC_X17_Y4_N7 3 " "Info: 6: + IC(0.000 ns) + CELL(0.621 ns) = 2.048 ns; Loc. = LC_X17_Y4_N7; Fanout = 3; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|cout'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "0.621 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella4~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|cout } "NODE_NAME" } "" } } { "db/cntr_afd.tdf" "" { Text "E:/老项目/数字移相信号发生器/fpga/db/cntr_afd.tdf" 125 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.158 ns) + CELL(0.292 ns) 3.498 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|is_buffer_wrapped~0 7 COMB LC_X20_Y4_N9 1 " "Info: 7: + IC(1.158 ns) + CELL(0.292 ns) = 3.498 ns; Loc. = LC_X20_Y4_N9; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|is_buffer_wrapped~0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "1.450 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|cout sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_buffer_wrapped~0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_acquisition_buffer.vhd" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.423 ns) + CELL(0.590 ns) 4.511 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|buffer_write_addr_adv_ena_int~54 8 COMB LC_X20_Y4_N2 7 " "Info: 8: + IC(0.423 ns) + CELL(0.590 ns) = 4.511 ns; Loc. = LC_X20_Y4_N2; Fanout = 7; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|buffer_write_addr_adv_ena_int~54'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "1.013 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_buffer_wrapped~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_addr_adv_ena_int~54 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.138 ns) + CELL(0.867 ns) 6.516 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|safe_q\[3\] 9 REG LC_X17_Y4_N3 6 " "Info: 9: + IC(1.138 ns) + CELL(0.867 ns) = 6.516 ns; Loc. = LC_X17_Y4_N3; Fanout = 6; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|safe_q\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "2.005 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_addr_adv_ena_int~54 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_afd.tdf" "" { Text "E:/老项目/数字移相信号发生器/fpga/db/cntr_afd.tdf" 99 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.268 ns ( 50.15 % ) " "Info: Total cell delay = 3.268 ns ( 50.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.248 ns ( 49.85 % ) " "Info: Total interconnect delay = 3.248 ns ( 49.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "6.516 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[1] sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella1~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella2~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella3~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella4~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|cout sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_buffer_wrapped~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_addr_adv_ena_int~54 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.516 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[1] sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella1~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella2~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella3~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella4~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|cout sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_buffer_wrapped~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_addr_adv_ena_int~54 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[3] } { 0.000ns 0.529ns 0.000ns 0.000ns 0.000ns 0.000ns 1.158ns 0.423ns 1.138ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.621ns 0.292ns 0.590ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.485 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_123 292 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 292; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { clk } "NODE_NAME" } "" } } { "phase_shift_sin.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.299 ns) + CELL(0.711 ns) 7.485 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|safe_q\[3\] 2 REG LC_X17_Y4_N3 6 " "Info: 2: + IC(5.299 ns) + CELL(0.711 ns) = 7.485 ns; Loc. = LC_X17_Y4_N3; Fanout = 6; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|safe_q\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "6.010 ns" { clk sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_afd.tdf" "" { Text "E:/老项目/数字移相信号发生器/fpga/db/cntr_afd.tdf" 99 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 29.21 % ) " "Info: Total cell delay = 2.186 ns ( 29.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.299 ns ( 70.79 % ) " "Info: Total interconnect delay = 5.299 ns ( 70.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "7.485 ns" { clk sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.485 ns" { clk clk~out0 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[3] } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.485 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_123 292 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 292; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { clk } "NODE_NAME" } "" } } { "phase_shift_sin.vhd" "" { Text "E:/老项目/数字移相信号发生器/fpga/phase_shift_sin.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.299 ns) + CELL(0.711 ns) 7.485 ns sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|safe_q\[1\] 2 REG LC_X17_Y4_N1 6 " "Info: 2: + IC(5.299 ns) + CELL(0.711 ns) = 7.485 ns; Loc. = LC_X17_Y4_N1; Fanout = 6; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_afd:auto_generated\|safe_q\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "6.010 ns" { clk sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "db/cntr_afd.tdf" "" { Text "E:/老项目/数字移相信号发生器/fpga/db/cntr_afd.tdf" 99 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 29.21 % ) " "Info: Total cell delay = 2.186 ns ( 29.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.299 ns ( 70.79 % ) " "Info: Total interconnect delay = 5.299 ns ( 70.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "7.485 ns" { clk sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.485 ns" { clk clk~out0 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[1] } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "7.485 ns" { clk sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.485 ns" { clk clk~out0 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[3] } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "7.485 ns" { clk sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.485 ns" { clk clk~out0 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[1] } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_afd.tdf" "" { Text "E:/老项目/数字移相信号发生器/fpga/db/cntr_afd.tdf" 99 8 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "db/cntr_afd.tdf" "" { Text "E:/老项目/数字移相信号发生器/fpga/db/cntr_afd.tdf" 99 8 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "6.516 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[1] sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella1~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella2~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella3~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella4~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|cout sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_buffer_wrapped~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_addr_adv_ena_int~54 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.516 ns" { sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[1] sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella1~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella2~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella3~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|counter_cella4~COUT sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|cout sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|is_buffer_wrapped~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|buffer_write_addr_adv_ena_int~54 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[3] } { 0.000ns 0.529ns 0.000ns 0.000ns 0.000ns 0.000ns 1.158ns 0.423ns 1.138ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.621ns 0.292ns 0.590ns 0.867ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "7.485 ns" { clk sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.485 ns" { clk clk~out0 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[3] } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "7.485 ns" { clk sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.485 ns" { clk clk~out0 sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[1] } { 0.000ns 0.000ns 5.299ns } { 0.000ns 1.475ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\] register sld_hub:sld_hub_inst\|hub_tdo 78.95 MHz 12.666 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 78.95 MHz between source register \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 12.666 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.072 ns + Longest register register " "Info: + Longest register to register delay is 6.072 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\] 1 REG LC_X20_Y9_N7 50 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y9_N7; Fanout = 50; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.444 ns) + CELL(0.590 ns) 2.034 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~13 2 COMB LC_X20_Y8_N0 1 " "Info: 2: + IC(1.444 ns) + CELL(0.590 ns) = 2.034 ns; Loc. = LC_X20_Y8_N0; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state~13'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "2.034 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 } "NODE_NAME" } "" } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1020 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.233 ns) + CELL(0.590 ns) 3.857 ns sld_hub:sld_hub_inst\|hub_tdo~1105 3 COMB LC_X20_Y9_N1 1 " "Info: 3: + IC(1.233 ns) + CELL(0.590 ns) = 3.857 ns; Loc. = LC_X20_Y9_N1; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~1105'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "1.823 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~1105 } "NODE_NAME" } "" } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.590 ns) 4.881 ns sld_hub:sld_hub_inst\|hub_tdo~1107 4 COMB LC_X20_Y9_N2 1 " "Info: 4: + IC(0.434 ns) + CELL(0.590 ns) = 4.881 ns; Loc. = LC_X20_Y9_N2; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~1107'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "1.024 ns" { sld_hub:sld_hub_inst|hub_tdo~1105 sld_hub:sld_hub_inst|hub_tdo~1107 } "NODE_NAME" } "" } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.453 ns) + CELL(0.738 ns) 6.072 ns sld_hub:sld_hub_inst\|hub_tdo 5 REG LC_X20_Y9_N0 1 " "Info: 5: + IC(0.453 ns) + CELL(0.738 ns) = 6.072 ns; Loc. = LC_X20_Y9_N0; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "1.191 ns" { sld_hub:sld_hub_inst|hub_tdo~1107 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.508 ns ( 41.30 % ) " "Info: Total cell delay = 2.508 ns ( 41.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.564 ns ( 58.70 % ) " "Info: Total interconnect delay = 3.564 ns ( 58.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "6.072 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~1105 sld_hub:sld_hub_inst|hub_tdo~1107 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.072 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~1105 sld_hub:sld_hub_inst|hub_tdo~1107 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.444ns 1.233ns 0.434ns 0.453ns } { 0.000ns 0.590ns 0.590ns 0.590ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.273 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.273 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 308 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 308; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.562 ns) + CELL(0.711 ns) 5.273 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X20_Y9_N0 1 " "Info: 2: + IC(4.562 ns) + CELL(0.711 ns) = 5.273 ns; Loc. = LC_X20_Y9_N0; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.48 % ) " "Info: Total cell delay = 0.711 ns ( 13.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.562 ns ( 86.52 % ) " "Info: Total interconnect delay = 4.562 ns ( 86.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.562ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.273 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.273 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 308 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 308; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.562 ns) + CELL(0.711 ns) 5.273 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\] 2 REG LC_X20_Y9_N7 50 " "Info: 2: + IC(4.562 ns) + CELL(0.711 ns) = 5.273 ns; Loc. = LC_X20_Y9_N7; Fanout = 50; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.48 % ) " "Info: Total cell delay = 0.711 ns ( 13.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.562 ns ( 86.52 % ) " "Info: Total interconnect delay = 4.562 ns ( 86.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } { 0.000ns 4.562ns } { 0.000ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.562ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } { 0.000ns 4.562ns } { 0.000ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 1035 -1 0 } } { "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" "" { Text "d:/altera/quartus51/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "6.072 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~1105 sld_hub:sld_hub_inst|hub_tdo~1107 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.072 ns" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 sld_hub:sld_hub_inst|hub_tdo~1105 sld_hub:sld_hub_inst|hub_tdo~1107 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.444ns 1.233ns 0.434ns 0.453ns } { 0.000ns 0.590ns 0.590ns 0.590ns 0.738ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.562ns } { 0.000ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "phase_shift_sin" "UNKNOWN" "V1" "E:/老项目/数字移相信号发生器/fpga/db/phase_shift_sin.quartus_db" { Floorplan "E:/老项目/数字移相信号发生器/fpga/" "" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.273 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] } { 0.000ns 4.562ns } { 0.000ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}