phase_shift_sin.vhd

实现低频率的移相信号发生器,才用DDS技术直接的合成

library ieee;
use ieee.std_logic_1164.all;

entity phase_shift_sin is
	port(fword,pword:in std_logic_vector(7 downto 0);
	     clk:in std_logic;
	     fout,pout:out std_logic_vector(7 downto 0));
end phase_shift_sin;

architecture behave of phase_shift_sin is

  component sin_rom is
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		q		    : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
  end component;
  component adder8 is
	PORT
	(
		dataa		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		datab		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
  end component;
  component adder32 is
	PORT
	(
		dataa		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		datab		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
	);
  end  component;

  signal fword1,fword2:std_logic_vector(31 downto 0);
  signal pword1,pword2:std_logic_vector(7 downto 0);
  signal faddr,paddr:std_logic_vector(7 downto 0); 

begin

  p1:process(clk,fword1,pword1)
  begin
    if rising_edge(clk) then
      fword2<=fword1;
      pword2<=pword1;
    end if;
  end process;
   
  faddr<=fword2(31 downto 24);
  paddr<=pword2;
  
  u1:adder32 port map("0000"&fword&"00000000000000000000",fword2,fword1);
  u2:adder8  port map(fword2(31 downto 24),pword,pword1);
  u3:sin_rom port map(faddr,clk,fout);
  u4:sin_rom port map(paddr,clk,pout);

end behave;