phase_shift_sin.fit.eqn

实现低频率的移相信号发生器,才用DDS技术直接的合成

RB2_q_b[0]_PORT_A_write_enable_reg = DFFE(RB2_q_b[0]_PORT_A_write_enable, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_write_enable = SB2L2;
RB2_q_b[0]_PORT_B_write_enable_reg = DFFE(RB2_q_b[0]_PORT_B_write_enable, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_clock_0 = GLOBAL(clk);
RB2_q_b[0]_clock_1 = GLOBAL(A1L5);
RB2_q_b[0]_PORT_B_data_out = MEMORY(RB2_q_b[0]_PORT_A_data_in_reg, RB2_q_b[0]_PORT_B_data_in_reg, RB2_q_b[0]_PORT_A_address_reg, RB2_q_b[0]_PORT_B_address_reg, RB2_q_b[0]_PORT_A_write_enable_reg, RB2_q_b[0]_PORT_B_write_enable_reg, , , RB2_q_b[0]_clock_0, RB2_q_b[0]_clock_1, , , , );
RB2_q_b[4] = RB2_q_b[0]_PORT_B_data_out[4];

--RB2_q_b[3] is sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[3] at M4K_X13_Y6
RB2_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB2_q_b[0]_PORT_A_data_in_reg = DFFE(RB2_q_b[0]_PORT_A_data_in, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_data_in = BUS(SB2_ram_rom_data_reg[0], SB2_ram_rom_data_reg[1], SB2_ram_rom_data_reg[2], SB2_ram_rom_data_reg[3], SB2_ram_rom_data_reg[4], SB2_ram_rom_data_reg[5], SB2_ram_rom_data_reg[6], SB2_ram_rom_data_reg[7]);
RB2_q_b[0]_PORT_B_data_in_reg = DFFE(RB2_q_b[0]_PORT_B_data_in, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_PORT_A_address = BUS(pword2[0], pword2[1], pword2[2], pword2[3], pword2[4], pword2[5], pword2[6], pword2[7]);
RB2_q_b[0]_PORT_A_address_reg = DFFE(RB2_q_b[0]_PORT_A_address, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_address = BUS(SB2_ram_rom_addr_reg[0], SB2_ram_rom_addr_reg[1], SB2_ram_rom_addr_reg[2], SB2_ram_rom_addr_reg[3], SB2_ram_rom_addr_reg[4], SB2_ram_rom_addr_reg[5], SB2_ram_rom_addr_reg[6], SB2_ram_rom_addr_reg[7]);
RB2_q_b[0]_PORT_B_address_reg = DFFE(RB2_q_b[0]_PORT_B_address, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_PORT_A_write_enable = GND;
RB2_q_b[0]_PORT_A_write_enable_reg = DFFE(RB2_q_b[0]_PORT_A_write_enable, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_write_enable = SB2L2;
RB2_q_b[0]_PORT_B_write_enable_reg = DFFE(RB2_q_b[0]_PORT_B_write_enable, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_clock_0 = GLOBAL(clk);
RB2_q_b[0]_clock_1 = GLOBAL(A1L5);
RB2_q_b[0]_PORT_B_data_out = MEMORY(RB2_q_b[0]_PORT_A_data_in_reg, RB2_q_b[0]_PORT_B_data_in_reg, RB2_q_b[0]_PORT_A_address_reg, RB2_q_b[0]_PORT_B_address_reg, RB2_q_b[0]_PORT_A_write_enable_reg, RB2_q_b[0]_PORT_B_write_enable_reg, , , RB2_q_b[0]_clock_0, RB2_q_b[0]_clock_1, , , , );
RB2_q_b[3] = RB2_q_b[0]_PORT_B_data_out[3];

--RB2_q_b[2] is sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[2] at M4K_X13_Y6
RB2_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB2_q_b[0]_PORT_A_data_in_reg = DFFE(RB2_q_b[0]_PORT_A_data_in, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_data_in = BUS(SB2_ram_rom_data_reg[0], SB2_ram_rom_data_reg[1], SB2_ram_rom_data_reg[2], SB2_ram_rom_data_reg[3], SB2_ram_rom_data_reg[4], SB2_ram_rom_data_reg[5], SB2_ram_rom_data_reg[6], SB2_ram_rom_data_reg[7]);
RB2_q_b[0]_PORT_B_data_in_reg = DFFE(RB2_q_b[0]_PORT_B_data_in, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_PORT_A_address = BUS(pword2[0], pword2[1], pword2[2], pword2[3], pword2[4], pword2[5], pword2[6], pword2[7]);
RB2_q_b[0]_PORT_A_address_reg = DFFE(RB2_q_b[0]_PORT_A_address, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_address = BUS(SB2_ram_rom_addr_reg[0], SB2_ram_rom_addr_reg[1], SB2_ram_rom_addr_reg[2], SB2_ram_rom_addr_reg[3], SB2_ram_rom_addr_reg[4], SB2_ram_rom_addr_reg[5], SB2_ram_rom_addr_reg[6], SB2_ram_rom_addr_reg[7]);
RB2_q_b[0]_PORT_B_address_reg = DFFE(RB2_q_b[0]_PORT_B_address, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_PORT_A_write_enable = GND;
RB2_q_b[0]_PORT_A_write_enable_reg = DFFE(RB2_q_b[0]_PORT_A_write_enable, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_write_enable = SB2L2;
RB2_q_b[0]_PORT_B_write_enable_reg = DFFE(RB2_q_b[0]_PORT_B_write_enable, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_clock_0 = GLOBAL(clk);
RB2_q_b[0]_clock_1 = GLOBAL(A1L5);
RB2_q_b[0]_PORT_B_data_out = MEMORY(RB2_q_b[0]_PORT_A_data_in_reg, RB2_q_b[0]_PORT_B_data_in_reg, RB2_q_b[0]_PORT_A_address_reg, RB2_q_b[0]_PORT_B_address_reg, RB2_q_b[0]_PORT_A_write_enable_reg, RB2_q_b[0]_PORT_B_write_enable_reg, , , RB2_q_b[0]_clock_0, RB2_q_b[0]_clock_1, , , , );
RB2_q_b[2] = RB2_q_b[0]_PORT_B_data_out[2];

--RB2_q_b[1] is sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[1] at M4K_X13_Y6
RB2_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB2_q_b[0]_PORT_A_data_in_reg = DFFE(RB2_q_b[0]_PORT_A_data_in, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_data_in = BUS(SB2_ram_rom_data_reg[0], SB2_ram_rom_data_reg[1], SB2_ram_rom_data_reg[2], SB2_ram_rom_data_reg[3], SB2_ram_rom_data_reg[4], SB2_ram_rom_data_reg[5], SB2_ram_rom_data_reg[6], SB2_ram_rom_data_reg[7]);
RB2_q_b[0]_PORT_B_data_in_reg = DFFE(RB2_q_b[0]_PORT_B_data_in, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_PORT_A_address = BUS(pword2[0], pword2[1], pword2[2], pword2[3], pword2[4], pword2[5], pword2[6], pword2[7]);
RB2_q_b[0]_PORT_A_address_reg = DFFE(RB2_q_b[0]_PORT_A_address, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_address = BUS(SB2_ram_rom_addr_reg[0], SB2_ram_rom_addr_reg[1], SB2_ram_rom_addr_reg[2], SB2_ram_rom_addr_reg[3], SB2_ram_rom_addr_reg[4], SB2_ram_rom_addr_reg[5], SB2_ram_rom_addr_reg[6], SB2_ram_rom_addr_reg[7]);
RB2_q_b[0]_PORT_B_address_reg = DFFE(RB2_q_b[0]_PORT_B_address, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_PORT_A_write_enable = GND;
RB2_q_b[0]_PORT_A_write_enable_reg = DFFE(RB2_q_b[0]_PORT_A_write_enable, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_write_enable = SB2L2;
RB2_q_b[0]_PORT_B_write_enable_reg = DFFE(RB2_q_b[0]_PORT_B_write_enable, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_clock_0 = GLOBAL(clk);
RB2_q_b[0]_clock_1 = GLOBAL(A1L5);
RB2_q_b[0]_PORT_B_data_out = MEMORY(RB2_q_b[0]_PORT_A_data_in_reg, RB2_q_b[0]_PORT_B_data_in_reg, RB2_q_b[0]_PORT_A_address_reg, RB2_q_b[0]_PORT_B_address_reg, RB2_q_b[0]_PORT_A_write_enable_reg, RB2_q_b[0]_PORT_B_write_enable_reg, , , RB2_q_b[0]_clock_0, RB2_q_b[0]_clock_1, , , , );
RB2_q_b[1] = RB2_q_b[0]_PORT_B_data_out[1];


--A1L6 is altera_internal_jtag~TDO at JTAG_X1_Y6_N1
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);

--A1L7 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y6_N1
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);

--A1L5 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y6_N1
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);

--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y6_N1
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !C1_hub_tdo);


--JB1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5] at LC_X20_Y8_N6
--operation mode is normal

JB1_state[5] = AMPP_FUNCTION(A1L5, JB1_state[4], JB1_state[3], A1L7, VCC);


--GB6_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] at LC_X19_Y8_N5
--operation mode is normal

GB6_Q[2] = AMPP_FUNCTION(A1L5, GB2_Q[0], GB3_Q[2], GB9_Q[2], C1_CLRN_SIGNAL, C1L29);


--GB10_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] at LC_X18_Y10_N3
--operation mode is normal

GB10_Q[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, GB3_Q[8], C1_CLRN_SIGNAL, C1L27);


--C1_jtag_debug_mode is sld_hub:sld_hub_inst|jtag_debug_mode at LC_X19_Y7_N5
--operation mode is normal

C1_jtag_debug_mode = AMPP_FUNCTION(A1L5, C1L42, C1L41, JB1_state[15], C1_jtag_debug_mode, JB1_state[0]);


--C1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1 at LC_X19_Y7_N8
--operation mode is normal

C1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L5, A1L108, N5_dffs[0], A1L107, N5_dffs[1], JB1_state[0], JB1_state[12]);


--GB2_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0] at LC_X20_Y8_N3
--operation mode is normal

GB2_Q[0] = AMPP_FUNCTION(A1L5, KB1_dffe1a[1], GB2_Q[0], C1L1, GB11_Q[0], C1_CLRN_SIGNAL);


--SB1L62 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~21 at LC_X19_Y8_N6
--operation mode is normal

SB1L62 = AMPP_FUNCTION(C1_jtag_debug_mode_usr1, C1_jtag_debug_mode, GB10_Q[0], GB2_Q[0]);


--SB1L2 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|enable_write~11 at LC_X17_Y8_N7
--operation mode is normal

SB1L2 = AMPP_FUNCTION(GB6_Q[2], JB1_state[5], SB1L62);


--fword2[24] is fword2[24] at LC_X12_Y9_N8
--operation mode is arithmetic

fword2[24]_carry_eqn = (!A1L27 & A1L35) # (A1L27 & A1L36);
fword2[24]_lut_out = fword[4] $ fword2[24] $ !fword2[24]_carry_eqn;
fword2[24] = DFFEAS(fword2[24]_lut_out, GLOBAL(clk), VCC, , , , , , );

--A1L38 is fword2[24]~85 at LC_X12_Y9_N8
--operation mode is arithmetic

A1L38_cout_0 = fword[4] & (fword2[24] # !A1L35) # !fword[4] & fword2[24]