phase_shift_sin.fit.eqn

实现低频率的移相信号发生器,才用DDS技术直接的合成

RB2_q_a[0]_PORT_A_data_in_reg = DFFE(RB2_q_a[0]_PORT_A_data_in, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_data_in = BUS(SB2_ram_rom_data_reg[0], SB2_ram_rom_data_reg[1], SB2_ram_rom_data_reg[2], SB2_ram_rom_data_reg[3], SB2_ram_rom_data_reg[4], SB2_ram_rom_data_reg[5], SB2_ram_rom_data_reg[6], SB2_ram_rom_data_reg[7]);
RB2_q_a[0]_PORT_B_data_in_reg = DFFE(RB2_q_a[0]_PORT_B_data_in, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_PORT_A_address = BUS(pword2[0], pword2[1], pword2[2], pword2[3], pword2[4], pword2[5], pword2[6], pword2[7]);
RB2_q_a[0]_PORT_A_address_reg = DFFE(RB2_q_a[0]_PORT_A_address, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_address = BUS(SB2_ram_rom_addr_reg[0], SB2_ram_rom_addr_reg[1], SB2_ram_rom_addr_reg[2], SB2_ram_rom_addr_reg[3], SB2_ram_rom_addr_reg[4], SB2_ram_rom_addr_reg[5], SB2_ram_rom_addr_reg[6], SB2_ram_rom_addr_reg[7]);
RB2_q_a[0]_PORT_B_address_reg = DFFE(RB2_q_a[0]_PORT_B_address, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_PORT_A_write_enable = GND;
RB2_q_a[0]_PORT_A_write_enable_reg = DFFE(RB2_q_a[0]_PORT_A_write_enable, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_write_enable = SB2L2;
RB2_q_a[0]_PORT_B_write_enable_reg = DFFE(RB2_q_a[0]_PORT_B_write_enable, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_clock_0 = GLOBAL(clk);
RB2_q_a[0]_clock_1 = GLOBAL(A1L5);
RB2_q_a[0]_PORT_A_data_out = MEMORY(RB2_q_a[0]_PORT_A_data_in_reg, RB2_q_a[0]_PORT_B_data_in_reg, RB2_q_a[0]_PORT_A_address_reg, RB2_q_a[0]_PORT_B_address_reg, RB2_q_a[0]_PORT_A_write_enable_reg, RB2_q_a[0]_PORT_B_write_enable_reg, , , RB2_q_a[0]_clock_0, RB2_q_a[0]_clock_1, , , , );
RB2_q_a[0]_PORT_A_data_out_reg = DFFE(RB2_q_a[0]_PORT_A_data_out, RB2_q_a[0]_clock_0, , , );
RB2_q_a[4] = RB2_q_a[0]_PORT_A_data_out_reg[4];

--RB2_q_a[3] is sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[3] at M4K_X13_Y6
RB2_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB2_q_a[0]_PORT_A_data_in_reg = DFFE(RB2_q_a[0]_PORT_A_data_in, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_data_in = BUS(SB2_ram_rom_data_reg[0], SB2_ram_rom_data_reg[1], SB2_ram_rom_data_reg[2], SB2_ram_rom_data_reg[3], SB2_ram_rom_data_reg[4], SB2_ram_rom_data_reg[5], SB2_ram_rom_data_reg[6], SB2_ram_rom_data_reg[7]);
RB2_q_a[0]_PORT_B_data_in_reg = DFFE(RB2_q_a[0]_PORT_B_data_in, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_PORT_A_address = BUS(pword2[0], pword2[1], pword2[2], pword2[3], pword2[4], pword2[5], pword2[6], pword2[7]);
RB2_q_a[0]_PORT_A_address_reg = DFFE(RB2_q_a[0]_PORT_A_address, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_address = BUS(SB2_ram_rom_addr_reg[0], SB2_ram_rom_addr_reg[1], SB2_ram_rom_addr_reg[2], SB2_ram_rom_addr_reg[3], SB2_ram_rom_addr_reg[4], SB2_ram_rom_addr_reg[5], SB2_ram_rom_addr_reg[6], SB2_ram_rom_addr_reg[7]);
RB2_q_a[0]_PORT_B_address_reg = DFFE(RB2_q_a[0]_PORT_B_address, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_PORT_A_write_enable = GND;
RB2_q_a[0]_PORT_A_write_enable_reg = DFFE(RB2_q_a[0]_PORT_A_write_enable, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_write_enable = SB2L2;
RB2_q_a[0]_PORT_B_write_enable_reg = DFFE(RB2_q_a[0]_PORT_B_write_enable, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_clock_0 = GLOBAL(clk);
RB2_q_a[0]_clock_1 = GLOBAL(A1L5);
RB2_q_a[0]_PORT_A_data_out = MEMORY(RB2_q_a[0]_PORT_A_data_in_reg, RB2_q_a[0]_PORT_B_data_in_reg, RB2_q_a[0]_PORT_A_address_reg, RB2_q_a[0]_PORT_B_address_reg, RB2_q_a[0]_PORT_A_write_enable_reg, RB2_q_a[0]_PORT_B_write_enable_reg, , , RB2_q_a[0]_clock_0, RB2_q_a[0]_clock_1, , , , );
RB2_q_a[0]_PORT_A_data_out_reg = DFFE(RB2_q_a[0]_PORT_A_data_out, RB2_q_a[0]_clock_0, , , );
RB2_q_a[3] = RB2_q_a[0]_PORT_A_data_out_reg[3];

--RB2_q_a[2] is sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[2] at M4K_X13_Y6
RB2_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB2_q_a[0]_PORT_A_data_in_reg = DFFE(RB2_q_a[0]_PORT_A_data_in, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_data_in = BUS(SB2_ram_rom_data_reg[0], SB2_ram_rom_data_reg[1], SB2_ram_rom_data_reg[2], SB2_ram_rom_data_reg[3], SB2_ram_rom_data_reg[4], SB2_ram_rom_data_reg[5], SB2_ram_rom_data_reg[6], SB2_ram_rom_data_reg[7]);
RB2_q_a[0]_PORT_B_data_in_reg = DFFE(RB2_q_a[0]_PORT_B_data_in, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_PORT_A_address = BUS(pword2[0], pword2[1], pword2[2], pword2[3], pword2[4], pword2[5], pword2[6], pword2[7]);
RB2_q_a[0]_PORT_A_address_reg = DFFE(RB2_q_a[0]_PORT_A_address, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_address = BUS(SB2_ram_rom_addr_reg[0], SB2_ram_rom_addr_reg[1], SB2_ram_rom_addr_reg[2], SB2_ram_rom_addr_reg[3], SB2_ram_rom_addr_reg[4], SB2_ram_rom_addr_reg[5], SB2_ram_rom_addr_reg[6], SB2_ram_rom_addr_reg[7]);
RB2_q_a[0]_PORT_B_address_reg = DFFE(RB2_q_a[0]_PORT_B_address, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_PORT_A_write_enable = GND;
RB2_q_a[0]_PORT_A_write_enable_reg = DFFE(RB2_q_a[0]_PORT_A_write_enable, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_write_enable = SB2L2;
RB2_q_a[0]_PORT_B_write_enable_reg = DFFE(RB2_q_a[0]_PORT_B_write_enable, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_clock_0 = GLOBAL(clk);
RB2_q_a[0]_clock_1 = GLOBAL(A1L5);
RB2_q_a[0]_PORT_A_data_out = MEMORY(RB2_q_a[0]_PORT_A_data_in_reg, RB2_q_a[0]_PORT_B_data_in_reg, RB2_q_a[0]_PORT_A_address_reg, RB2_q_a[0]_PORT_B_address_reg, RB2_q_a[0]_PORT_A_write_enable_reg, RB2_q_a[0]_PORT_B_write_enable_reg, , , RB2_q_a[0]_clock_0, RB2_q_a[0]_clock_1, , , , );
RB2_q_a[0]_PORT_A_data_out_reg = DFFE(RB2_q_a[0]_PORT_A_data_out, RB2_q_a[0]_clock_0, , , );
RB2_q_a[2] = RB2_q_a[0]_PORT_A_data_out_reg[2];

--RB2_q_a[1] is sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[1] at M4K_X13_Y6
RB2_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB2_q_a[0]_PORT_A_data_in_reg = DFFE(RB2_q_a[0]_PORT_A_data_in, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_data_in = BUS(SB2_ram_rom_data_reg[0], SB2_ram_rom_data_reg[1], SB2_ram_rom_data_reg[2], SB2_ram_rom_data_reg[3], SB2_ram_rom_data_reg[4], SB2_ram_rom_data_reg[5], SB2_ram_rom_data_reg[6], SB2_ram_rom_data_reg[7]);
RB2_q_a[0]_PORT_B_data_in_reg = DFFE(RB2_q_a[0]_PORT_B_data_in, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_PORT_A_address = BUS(pword2[0], pword2[1], pword2[2], pword2[3], pword2[4], pword2[5], pword2[6], pword2[7]);
RB2_q_a[0]_PORT_A_address_reg = DFFE(RB2_q_a[0]_PORT_A_address, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_address = BUS(SB2_ram_rom_addr_reg[0], SB2_ram_rom_addr_reg[1], SB2_ram_rom_addr_reg[2], SB2_ram_rom_addr_reg[3], SB2_ram_rom_addr_reg[4], SB2_ram_rom_addr_reg[5], SB2_ram_rom_addr_reg[6], SB2_ram_rom_addr_reg[7]);
RB2_q_a[0]_PORT_B_address_reg = DFFE(RB2_q_a[0]_PORT_B_address, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_PORT_A_write_enable = GND;
RB2_q_a[0]_PORT_A_write_enable_reg = DFFE(RB2_q_a[0]_PORT_A_write_enable, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_write_enable = SB2L2;
RB2_q_a[0]_PORT_B_write_enable_reg = DFFE(RB2_q_a[0]_PORT_B_write_enable, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_clock_0 = GLOBAL(clk);
RB2_q_a[0]_clock_1 = GLOBAL(A1L5);
RB2_q_a[0]_PORT_A_data_out = MEMORY(RB2_q_a[0]_PORT_A_data_in_reg, RB2_q_a[0]_PORT_B_data_in_reg, RB2_q_a[0]_PORT_A_address_reg, RB2_q_a[0]_PORT_B_address_reg, RB2_q_a[0]_PORT_A_write_enable_reg, RB2_q_a[0]_PORT_B_write_enable_reg, , , RB2_q_a[0]_clock_0, RB2_q_a[0]_clock_1, , , , );
RB2_q_a[0]_PORT_A_data_out_reg = DFFE(RB2_q_a[0]_PORT_A_data_out, RB2_q_a[0]_clock_0, , , );
RB2_q_a[1] = RB2_q_a[0]_PORT_A_data_out_reg[1];

--RB2_q_b[7] is sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[7] at M4K_X13_Y6
RB2_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB2_q_b[0]_PORT_A_data_in_reg = DFFE(RB2_q_b[0]_PORT_A_data_in, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_data_in = BUS(SB2_ram_rom_data_reg[0], SB2_ram_rom_data_reg[1], SB2_ram_rom_data_reg[2], SB2_ram_rom_data_reg[3], SB2_ram_rom_data_reg[4], SB2_ram_rom_data_reg[5], SB2_ram_rom_data_reg[6], SB2_ram_rom_data_reg[7]);
RB2_q_b[0]_PORT_B_data_in_reg = DFFE(RB2_q_b[0]_PORT_B_data_in, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_PORT_A_address = BUS(pword2[0], pword2[1], pword2[2], pword2[3], pword2[4], pword2[5], pword2[6], pword2[7]);
RB2_q_b[0]_PORT_A_address_reg = DFFE(RB2_q_b[0]_PORT_A_address, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_address = BUS(SB2_ram_rom_addr_reg[0], SB2_ram_rom_addr_reg[1], SB2_ram_rom_addr_reg[2], SB2_ram_rom_addr_reg[3], SB2_ram_rom_addr_reg[4], SB2_ram_rom_addr_reg[5], SB2_ram_rom_addr_reg[6], SB2_ram_rom_addr_reg[7]);
RB2_q_b[0]_PORT_B_address_reg = DFFE(RB2_q_b[0]_PORT_B_address, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_PORT_A_write_enable = GND;
RB2_q_b[0]_PORT_A_write_enable_reg = DFFE(RB2_q_b[0]_PORT_A_write_enable, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_write_enable = SB2L2;
RB2_q_b[0]_PORT_B_write_enable_reg = DFFE(RB2_q_b[0]_PORT_B_write_enable, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_clock_0 = GLOBAL(clk);
RB2_q_b[0]_clock_1 = GLOBAL(A1L5);
RB2_q_b[0]_PORT_B_data_out = MEMORY(RB2_q_b[0]_PORT_A_data_in_reg, RB2_q_b[0]_PORT_B_data_in_reg, RB2_q_b[0]_PORT_A_address_reg, RB2_q_b[0]_PORT_B_address_reg, RB2_q_b[0]_PORT_A_write_enable_reg, RB2_q_b[0]_PORT_B_write_enable_reg, , , RB2_q_b[0]_clock_0, RB2_q_b[0]_clock_1, , , , );
RB2_q_b[7] = RB2_q_b[0]_PORT_B_data_out[7];

--RB2_q_b[6] is sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[6] at M4K_X13_Y6
RB2_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB2_q_b[0]_PORT_A_data_in_reg = DFFE(RB2_q_b[0]_PORT_A_data_in, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_data_in = BUS(SB2_ram_rom_data_reg[0], SB2_ram_rom_data_reg[1], SB2_ram_rom_data_reg[2], SB2_ram_rom_data_reg[3], SB2_ram_rom_data_reg[4], SB2_ram_rom_data_reg[5], SB2_ram_rom_data_reg[6], SB2_ram_rom_data_reg[7]);
RB2_q_b[0]_PORT_B_data_in_reg = DFFE(RB2_q_b[0]_PORT_B_data_in, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_PORT_A_address = BUS(pword2[0], pword2[1], pword2[2], pword2[3], pword2[4], pword2[5], pword2[6], pword2[7]);
RB2_q_b[0]_PORT_A_address_reg = DFFE(RB2_q_b[0]_PORT_A_address, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_address = BUS(SB2_ram_rom_addr_reg[0], SB2_ram_rom_addr_reg[1], SB2_ram_rom_addr_reg[2], SB2_ram_rom_addr_reg[3], SB2_ram_rom_addr_reg[4], SB2_ram_rom_addr_reg[5], SB2_ram_rom_addr_reg[6], SB2_ram_rom_addr_reg[7]);
RB2_q_b[0]_PORT_B_address_reg = DFFE(RB2_q_b[0]_PORT_B_address, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_PORT_A_write_enable = GND;
RB2_q_b[0]_PORT_A_write_enable_reg = DFFE(RB2_q_b[0]_PORT_A_write_enable, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_write_enable = SB2L2;
RB2_q_b[0]_PORT_B_write_enable_reg = DFFE(RB2_q_b[0]_PORT_B_write_enable, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_clock_0 = GLOBAL(clk);
RB2_q_b[0]_clock_1 = GLOBAL(A1L5);
RB2_q_b[0]_PORT_B_data_out = MEMORY(RB2_q_b[0]_PORT_A_data_in_reg, RB2_q_b[0]_PORT_B_data_in_reg, RB2_q_b[0]_PORT_A_address_reg, RB2_q_b[0]_PORT_B_address_reg, RB2_q_b[0]_PORT_A_write_enable_reg, RB2_q_b[0]_PORT_B_write_enable_reg, , , RB2_q_b[0]_clock_0, RB2_q_b[0]_clock_1, , , , );
RB2_q_b[6] = RB2_q_b[0]_PORT_B_data_out[6];

--RB2_q_b[5] is sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[5] at M4K_X13_Y6
RB2_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB2_q_b[0]_PORT_A_data_in_reg = DFFE(RB2_q_b[0]_PORT_A_data_in, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_data_in = BUS(SB2_ram_rom_data_reg[0], SB2_ram_rom_data_reg[1], SB2_ram_rom_data_reg[2], SB2_ram_rom_data_reg[3], SB2_ram_rom_data_reg[4], SB2_ram_rom_data_reg[5], SB2_ram_rom_data_reg[6], SB2_ram_rom_data_reg[7]);
RB2_q_b[0]_PORT_B_data_in_reg = DFFE(RB2_q_b[0]_PORT_B_data_in, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_PORT_A_address = BUS(pword2[0], pword2[1], pword2[2], pword2[3], pword2[4], pword2[5], pword2[6], pword2[7]);
RB2_q_b[0]_PORT_A_address_reg = DFFE(RB2_q_b[0]_PORT_A_address, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_address = BUS(SB2_ram_rom_addr_reg[0], SB2_ram_rom_addr_reg[1], SB2_ram_rom_addr_reg[2], SB2_ram_rom_addr_reg[3], SB2_ram_rom_addr_reg[4], SB2_ram_rom_addr_reg[5], SB2_ram_rom_addr_reg[6], SB2_ram_rom_addr_reg[7]);
RB2_q_b[0]_PORT_B_address_reg = DFFE(RB2_q_b[0]_PORT_B_address, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_PORT_A_write_enable = GND;
RB2_q_b[0]_PORT_A_write_enable_reg = DFFE(RB2_q_b[0]_PORT_A_write_enable, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_write_enable = SB2L2;
RB2_q_b[0]_PORT_B_write_enable_reg = DFFE(RB2_q_b[0]_PORT_B_write_enable, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_clock_0 = GLOBAL(clk);
RB2_q_b[0]_clock_1 = GLOBAL(A1L5);
RB2_q_b[0]_PORT_B_data_out = MEMORY(RB2_q_b[0]_PORT_A_data_in_reg, RB2_q_b[0]_PORT_B_data_in_reg, RB2_q_b[0]_PORT_A_address_reg, RB2_q_b[0]_PORT_B_address_reg, RB2_q_b[0]_PORT_A_write_enable_reg, RB2_q_b[0]_PORT_B_write_enable_reg, , , RB2_q_b[0]_clock_0, RB2_q_b[0]_clock_1, , , , );
RB2_q_b[5] = RB2_q_b[0]_PORT_B_data_out[5];

--RB2_q_b[4] is sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[4] at M4K_X13_Y6
RB2_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB2_q_b[0]_PORT_A_data_in_reg = DFFE(RB2_q_b[0]_PORT_A_data_in, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_data_in = BUS(SB2_ram_rom_data_reg[0], SB2_ram_rom_data_reg[1], SB2_ram_rom_data_reg[2], SB2_ram_rom_data_reg[3], SB2_ram_rom_data_reg[4], SB2_ram_rom_data_reg[5], SB2_ram_rom_data_reg[6], SB2_ram_rom_data_reg[7]);
RB2_q_b[0]_PORT_B_data_in_reg = DFFE(RB2_q_b[0]_PORT_B_data_in, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_PORT_A_address = BUS(pword2[0], pword2[1], pword2[2], pword2[3], pword2[4], pword2[5], pword2[6], pword2[7]);
RB2_q_b[0]_PORT_A_address_reg = DFFE(RB2_q_b[0]_PORT_A_address, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_address = BUS(SB2_ram_rom_addr_reg[0], SB2_ram_rom_addr_reg[1], SB2_ram_rom_addr_reg[2], SB2_ram_rom_addr_reg[3], SB2_ram_rom_addr_reg[4], SB2_ram_rom_addr_reg[5], SB2_ram_rom_addr_reg[6], SB2_ram_rom_addr_reg[7]);
RB2_q_b[0]_PORT_B_address_reg = DFFE(RB2_q_b[0]_PORT_B_address, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_PORT_A_write_enable = GND;