phase_shift_sin.fit.eqn

实现低频率的移相信号发生器,才用DDS技术直接的合成

--RB1_q_b[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[2] at M4K_X13_Y8
RB1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB1_q_b[0]_PORT_A_data_in_reg = DFFE(RB1_q_b[0]_PORT_A_data_in, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[0], SB1_ram_rom_data_reg[1], SB1_ram_rom_data_reg[2], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[5], SB1_ram_rom_data_reg[6], SB1_ram_rom_data_reg[7]);
RB1_q_b[0]_PORT_B_data_in_reg = DFFE(RB1_q_b[0]_PORT_B_data_in, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_b[0]_PORT_A_address_reg = DFFE(RB1_q_b[0]_PORT_A_address, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_b[0]_PORT_B_address_reg = DFFE(RB1_q_b[0]_PORT_B_address, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_PORT_A_write_enable = GND;
RB1_q_b[0]_PORT_A_write_enable_reg = DFFE(RB1_q_b[0]_PORT_A_write_enable, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_write_enable = SB1L2;
RB1_q_b[0]_PORT_B_write_enable_reg = DFFE(RB1_q_b[0]_PORT_B_write_enable, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_clock_0 = GLOBAL(clk);
RB1_q_b[0]_clock_1 = GLOBAL(A1L5);
RB1_q_b[0]_PORT_B_data_out = MEMORY(RB1_q_b[0]_PORT_A_data_in_reg, RB1_q_b[0]_PORT_B_data_in_reg, RB1_q_b[0]_PORT_A_address_reg, RB1_q_b[0]_PORT_B_address_reg, RB1_q_b[0]_PORT_A_write_enable_reg, RB1_q_b[0]_PORT_B_write_enable_reg, , , RB1_q_b[0]_clock_0, RB1_q_b[0]_clock_1, , , , );
RB1_q_b[2] = RB1_q_b[0]_PORT_B_data_out[2];

--RB1_q_b[1] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[1] at M4K_X13_Y8
RB1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB1_q_b[0]_PORT_A_data_in_reg = DFFE(RB1_q_b[0]_PORT_A_data_in, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[0], SB1_ram_rom_data_reg[1], SB1_ram_rom_data_reg[2], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[5], SB1_ram_rom_data_reg[6], SB1_ram_rom_data_reg[7]);
RB1_q_b[0]_PORT_B_data_in_reg = DFFE(RB1_q_b[0]_PORT_B_data_in, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_b[0]_PORT_A_address_reg = DFFE(RB1_q_b[0]_PORT_A_address, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_b[0]_PORT_B_address_reg = DFFE(RB1_q_b[0]_PORT_B_address, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_PORT_A_write_enable = GND;
RB1_q_b[0]_PORT_A_write_enable_reg = DFFE(RB1_q_b[0]_PORT_A_write_enable, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_write_enable = SB1L2;
RB1_q_b[0]_PORT_B_write_enable_reg = DFFE(RB1_q_b[0]_PORT_B_write_enable, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_clock_0 = GLOBAL(clk);
RB1_q_b[0]_clock_1 = GLOBAL(A1L5);
RB1_q_b[0]_PORT_B_data_out = MEMORY(RB1_q_b[0]_PORT_A_data_in_reg, RB1_q_b[0]_PORT_B_data_in_reg, RB1_q_b[0]_PORT_A_address_reg, RB1_q_b[0]_PORT_B_address_reg, RB1_q_b[0]_PORT_A_write_enable_reg, RB1_q_b[0]_PORT_B_write_enable_reg, , , RB1_q_b[0]_clock_0, RB1_q_b[0]_clock_1, , , , );
RB1_q_b[1] = RB1_q_b[0]_PORT_B_data_out[1];


--RB2_q_a[0] is sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] at M4K_X13_Y6
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 8, Port B Depth: 256, Port B Width: 8
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
RB2_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB2_q_a[0]_PORT_A_data_in_reg = DFFE(RB2_q_a[0]_PORT_A_data_in, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_data_in = BUS(SB2_ram_rom_data_reg[0], SB2_ram_rom_data_reg[1], SB2_ram_rom_data_reg[2], SB2_ram_rom_data_reg[3], SB2_ram_rom_data_reg[4], SB2_ram_rom_data_reg[5], SB2_ram_rom_data_reg[6], SB2_ram_rom_data_reg[7]);
RB2_q_a[0]_PORT_B_data_in_reg = DFFE(RB2_q_a[0]_PORT_B_data_in, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_PORT_A_address = BUS(pword2[0], pword2[1], pword2[2], pword2[3], pword2[4], pword2[5], pword2[6], pword2[7]);
RB2_q_a[0]_PORT_A_address_reg = DFFE(RB2_q_a[0]_PORT_A_address, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_address = BUS(SB2_ram_rom_addr_reg[0], SB2_ram_rom_addr_reg[1], SB2_ram_rom_addr_reg[2], SB2_ram_rom_addr_reg[3], SB2_ram_rom_addr_reg[4], SB2_ram_rom_addr_reg[5], SB2_ram_rom_addr_reg[6], SB2_ram_rom_addr_reg[7]);
RB2_q_a[0]_PORT_B_address_reg = DFFE(RB2_q_a[0]_PORT_B_address, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_PORT_A_write_enable = GND;
RB2_q_a[0]_PORT_A_write_enable_reg = DFFE(RB2_q_a[0]_PORT_A_write_enable, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_write_enable = SB2L2;
RB2_q_a[0]_PORT_B_write_enable_reg = DFFE(RB2_q_a[0]_PORT_B_write_enable, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_clock_0 = GLOBAL(clk);
RB2_q_a[0]_clock_1 = GLOBAL(A1L5);
RB2_q_a[0]_PORT_A_data_out = MEMORY(RB2_q_a[0]_PORT_A_data_in_reg, RB2_q_a[0]_PORT_B_data_in_reg, RB2_q_a[0]_PORT_A_address_reg, RB2_q_a[0]_PORT_B_address_reg, RB2_q_a[0]_PORT_A_write_enable_reg, RB2_q_a[0]_PORT_B_write_enable_reg, , , RB2_q_a[0]_clock_0, RB2_q_a[0]_clock_1, , , , );
RB2_q_a[0]_PORT_A_data_out_reg = DFFE(RB2_q_a[0]_PORT_A_data_out, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0] = RB2_q_a[0]_PORT_A_data_out_reg[0];

--RB2_q_b[0] is sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[0] at M4K_X13_Y6
RB2_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB2_q_b[0]_PORT_A_data_in_reg = DFFE(RB2_q_b[0]_PORT_A_data_in, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_data_in = BUS(SB2_ram_rom_data_reg[0], SB2_ram_rom_data_reg[1], SB2_ram_rom_data_reg[2], SB2_ram_rom_data_reg[3], SB2_ram_rom_data_reg[4], SB2_ram_rom_data_reg[5], SB2_ram_rom_data_reg[6], SB2_ram_rom_data_reg[7]);
RB2_q_b[0]_PORT_B_data_in_reg = DFFE(RB2_q_b[0]_PORT_B_data_in, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_PORT_A_address = BUS(pword2[0], pword2[1], pword2[2], pword2[3], pword2[4], pword2[5], pword2[6], pword2[7]);
RB2_q_b[0]_PORT_A_address_reg = DFFE(RB2_q_b[0]_PORT_A_address, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_address = BUS(SB2_ram_rom_addr_reg[0], SB2_ram_rom_addr_reg[1], SB2_ram_rom_addr_reg[2], SB2_ram_rom_addr_reg[3], SB2_ram_rom_addr_reg[4], SB2_ram_rom_addr_reg[5], SB2_ram_rom_addr_reg[6], SB2_ram_rom_addr_reg[7]);
RB2_q_b[0]_PORT_B_address_reg = DFFE(RB2_q_b[0]_PORT_B_address, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_PORT_A_write_enable = GND;
RB2_q_b[0]_PORT_A_write_enable_reg = DFFE(RB2_q_b[0]_PORT_A_write_enable, RB2_q_b[0]_clock_0, , , );
RB2_q_b[0]_PORT_B_write_enable = SB2L2;
RB2_q_b[0]_PORT_B_write_enable_reg = DFFE(RB2_q_b[0]_PORT_B_write_enable, RB2_q_b[0]_clock_1, , , );
RB2_q_b[0]_clock_0 = GLOBAL(clk);
RB2_q_b[0]_clock_1 = GLOBAL(A1L5);
RB2_q_b[0]_PORT_B_data_out = MEMORY(RB2_q_b[0]_PORT_A_data_in_reg, RB2_q_b[0]_PORT_B_data_in_reg, RB2_q_b[0]_PORT_A_address_reg, RB2_q_b[0]_PORT_B_address_reg, RB2_q_b[0]_PORT_A_write_enable_reg, RB2_q_b[0]_PORT_B_write_enable_reg, , , RB2_q_b[0]_clock_0, RB2_q_b[0]_clock_1, , , , );
RB2_q_b[0] = RB2_q_b[0]_PORT_B_data_out[0];

--RB2_q_a[7] is sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[7] at M4K_X13_Y6
RB2_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB2_q_a[0]_PORT_A_data_in_reg = DFFE(RB2_q_a[0]_PORT_A_data_in, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_data_in = BUS(SB2_ram_rom_data_reg[0], SB2_ram_rom_data_reg[1], SB2_ram_rom_data_reg[2], SB2_ram_rom_data_reg[3], SB2_ram_rom_data_reg[4], SB2_ram_rom_data_reg[5], SB2_ram_rom_data_reg[6], SB2_ram_rom_data_reg[7]);
RB2_q_a[0]_PORT_B_data_in_reg = DFFE(RB2_q_a[0]_PORT_B_data_in, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_PORT_A_address = BUS(pword2[0], pword2[1], pword2[2], pword2[3], pword2[4], pword2[5], pword2[6], pword2[7]);
RB2_q_a[0]_PORT_A_address_reg = DFFE(RB2_q_a[0]_PORT_A_address, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_address = BUS(SB2_ram_rom_addr_reg[0], SB2_ram_rom_addr_reg[1], SB2_ram_rom_addr_reg[2], SB2_ram_rom_addr_reg[3], SB2_ram_rom_addr_reg[4], SB2_ram_rom_addr_reg[5], SB2_ram_rom_addr_reg[6], SB2_ram_rom_addr_reg[7]);
RB2_q_a[0]_PORT_B_address_reg = DFFE(RB2_q_a[0]_PORT_B_address, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_PORT_A_write_enable = GND;
RB2_q_a[0]_PORT_A_write_enable_reg = DFFE(RB2_q_a[0]_PORT_A_write_enable, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_write_enable = SB2L2;
RB2_q_a[0]_PORT_B_write_enable_reg = DFFE(RB2_q_a[0]_PORT_B_write_enable, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_clock_0 = GLOBAL(clk);
RB2_q_a[0]_clock_1 = GLOBAL(A1L5);
RB2_q_a[0]_PORT_A_data_out = MEMORY(RB2_q_a[0]_PORT_A_data_in_reg, RB2_q_a[0]_PORT_B_data_in_reg, RB2_q_a[0]_PORT_A_address_reg, RB2_q_a[0]_PORT_B_address_reg, RB2_q_a[0]_PORT_A_write_enable_reg, RB2_q_a[0]_PORT_B_write_enable_reg, , , RB2_q_a[0]_clock_0, RB2_q_a[0]_clock_1, , , , );
RB2_q_a[0]_PORT_A_data_out_reg = DFFE(RB2_q_a[0]_PORT_A_data_out, RB2_q_a[0]_clock_0, , , );
RB2_q_a[7] = RB2_q_a[0]_PORT_A_data_out_reg[7];

--RB2_q_a[6] is sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[6] at M4K_X13_Y6
RB2_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB2_q_a[0]_PORT_A_data_in_reg = DFFE(RB2_q_a[0]_PORT_A_data_in, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_data_in = BUS(SB2_ram_rom_data_reg[0], SB2_ram_rom_data_reg[1], SB2_ram_rom_data_reg[2], SB2_ram_rom_data_reg[3], SB2_ram_rom_data_reg[4], SB2_ram_rom_data_reg[5], SB2_ram_rom_data_reg[6], SB2_ram_rom_data_reg[7]);
RB2_q_a[0]_PORT_B_data_in_reg = DFFE(RB2_q_a[0]_PORT_B_data_in, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_PORT_A_address = BUS(pword2[0], pword2[1], pword2[2], pword2[3], pword2[4], pword2[5], pword2[6], pword2[7]);
RB2_q_a[0]_PORT_A_address_reg = DFFE(RB2_q_a[0]_PORT_A_address, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_address = BUS(SB2_ram_rom_addr_reg[0], SB2_ram_rom_addr_reg[1], SB2_ram_rom_addr_reg[2], SB2_ram_rom_addr_reg[3], SB2_ram_rom_addr_reg[4], SB2_ram_rom_addr_reg[5], SB2_ram_rom_addr_reg[6], SB2_ram_rom_addr_reg[7]);
RB2_q_a[0]_PORT_B_address_reg = DFFE(RB2_q_a[0]_PORT_B_address, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_PORT_A_write_enable = GND;
RB2_q_a[0]_PORT_A_write_enable_reg = DFFE(RB2_q_a[0]_PORT_A_write_enable, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_write_enable = SB2L2;
RB2_q_a[0]_PORT_B_write_enable_reg = DFFE(RB2_q_a[0]_PORT_B_write_enable, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_clock_0 = GLOBAL(clk);
RB2_q_a[0]_clock_1 = GLOBAL(A1L5);
RB2_q_a[0]_PORT_A_data_out = MEMORY(RB2_q_a[0]_PORT_A_data_in_reg, RB2_q_a[0]_PORT_B_data_in_reg, RB2_q_a[0]_PORT_A_address_reg, RB2_q_a[0]_PORT_B_address_reg, RB2_q_a[0]_PORT_A_write_enable_reg, RB2_q_a[0]_PORT_B_write_enable_reg, , , RB2_q_a[0]_clock_0, RB2_q_a[0]_clock_1, , , , );
RB2_q_a[0]_PORT_A_data_out_reg = DFFE(RB2_q_a[0]_PORT_A_data_out, RB2_q_a[0]_clock_0, , , );
RB2_q_a[6] = RB2_q_a[0]_PORT_A_data_out_reg[6];

--RB2_q_a[5] is sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[5] at M4K_X13_Y6
RB2_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB2_q_a[0]_PORT_A_data_in_reg = DFFE(RB2_q_a[0]_PORT_A_data_in, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_data_in = BUS(SB2_ram_rom_data_reg[0], SB2_ram_rom_data_reg[1], SB2_ram_rom_data_reg[2], SB2_ram_rom_data_reg[3], SB2_ram_rom_data_reg[4], SB2_ram_rom_data_reg[5], SB2_ram_rom_data_reg[6], SB2_ram_rom_data_reg[7]);
RB2_q_a[0]_PORT_B_data_in_reg = DFFE(RB2_q_a[0]_PORT_B_data_in, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_PORT_A_address = BUS(pword2[0], pword2[1], pword2[2], pword2[3], pword2[4], pword2[5], pword2[6], pword2[7]);
RB2_q_a[0]_PORT_A_address_reg = DFFE(RB2_q_a[0]_PORT_A_address, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_address = BUS(SB2_ram_rom_addr_reg[0], SB2_ram_rom_addr_reg[1], SB2_ram_rom_addr_reg[2], SB2_ram_rom_addr_reg[3], SB2_ram_rom_addr_reg[4], SB2_ram_rom_addr_reg[5], SB2_ram_rom_addr_reg[6], SB2_ram_rom_addr_reg[7]);
RB2_q_a[0]_PORT_B_address_reg = DFFE(RB2_q_a[0]_PORT_B_address, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_PORT_A_write_enable = GND;
RB2_q_a[0]_PORT_A_write_enable_reg = DFFE(RB2_q_a[0]_PORT_A_write_enable, RB2_q_a[0]_clock_0, , , );
RB2_q_a[0]_PORT_B_write_enable = SB2L2;
RB2_q_a[0]_PORT_B_write_enable_reg = DFFE(RB2_q_a[0]_PORT_B_write_enable, RB2_q_a[0]_clock_1, , , );
RB2_q_a[0]_clock_0 = GLOBAL(clk);
RB2_q_a[0]_clock_1 = GLOBAL(A1L5);
RB2_q_a[0]_PORT_A_data_out = MEMORY(RB2_q_a[0]_PORT_A_data_in_reg, RB2_q_a[0]_PORT_B_data_in_reg, RB2_q_a[0]_PORT_A_address_reg, RB2_q_a[0]_PORT_B_address_reg, RB2_q_a[0]_PORT_A_write_enable_reg, RB2_q_a[0]_PORT_B_write_enable_reg, , , RB2_q_a[0]_clock_0, RB2_q_a[0]_clock_1, , , , );
RB2_q_a[0]_PORT_A_data_out_reg = DFFE(RB2_q_a[0]_PORT_A_data_out, RB2_q_a[0]_clock_0, , , );
RB2_q_a[5] = RB2_q_a[0]_PORT_A_data_out_reg[5];

--RB2_q_a[4] is sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[4] at M4K_X13_Y6
RB2_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);