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📄 phase_shift_sin.fit.eqn

📁 实现低频率的移相信号发生器,才用DDS技术直接的合成
💻 EQN
📖 第 1 页 / 共 5 页
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RB1_q_a[0]_PORT_B_address_reg = DFFE(RB1_q_a[0]_PORT_B_address, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_PORT_A_write_enable = GND;
RB1_q_a[0]_PORT_A_write_enable_reg = DFFE(RB1_q_a[0]_PORT_A_write_enable, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_write_enable = SB1L2;
RB1_q_a[0]_PORT_B_write_enable_reg = DFFE(RB1_q_a[0]_PORT_B_write_enable, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_clock_0 = GLOBAL(clk);
RB1_q_a[0]_clock_1 = GLOBAL(A1L5);
RB1_q_a[0]_PORT_A_data_out = MEMORY(RB1_q_a[0]_PORT_A_data_in_reg, RB1_q_a[0]_PORT_B_data_in_reg, RB1_q_a[0]_PORT_A_address_reg, RB1_q_a[0]_PORT_B_address_reg, RB1_q_a[0]_PORT_A_write_enable_reg, RB1_q_a[0]_PORT_B_write_enable_reg, , , RB1_q_a[0]_clock_0, RB1_q_a[0]_clock_1, , , , );
RB1_q_a[0]_PORT_A_data_out_reg = DFFE(RB1_q_a[0]_PORT_A_data_out, RB1_q_a[0]_clock_0, , , );
RB1_q_a[3] = RB1_q_a[0]_PORT_A_data_out_reg[3];

--RB1_q_a[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[2] at M4K_X13_Y8
RB1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB1_q_a[0]_PORT_A_data_in_reg = DFFE(RB1_q_a[0]_PORT_A_data_in, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[0], SB1_ram_rom_data_reg[1], SB1_ram_rom_data_reg[2], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[5], SB1_ram_rom_data_reg[6], SB1_ram_rom_data_reg[7]);
RB1_q_a[0]_PORT_B_data_in_reg = DFFE(RB1_q_a[0]_PORT_B_data_in, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_a[0]_PORT_A_address_reg = DFFE(RB1_q_a[0]_PORT_A_address, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_a[0]_PORT_B_address_reg = DFFE(RB1_q_a[0]_PORT_B_address, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_PORT_A_write_enable = GND;
RB1_q_a[0]_PORT_A_write_enable_reg = DFFE(RB1_q_a[0]_PORT_A_write_enable, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_write_enable = SB1L2;
RB1_q_a[0]_PORT_B_write_enable_reg = DFFE(RB1_q_a[0]_PORT_B_write_enable, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_clock_0 = GLOBAL(clk);
RB1_q_a[0]_clock_1 = GLOBAL(A1L5);
RB1_q_a[0]_PORT_A_data_out = MEMORY(RB1_q_a[0]_PORT_A_data_in_reg, RB1_q_a[0]_PORT_B_data_in_reg, RB1_q_a[0]_PORT_A_address_reg, RB1_q_a[0]_PORT_B_address_reg, RB1_q_a[0]_PORT_A_write_enable_reg, RB1_q_a[0]_PORT_B_write_enable_reg, , , RB1_q_a[0]_clock_0, RB1_q_a[0]_clock_1, , , , );
RB1_q_a[0]_PORT_A_data_out_reg = DFFE(RB1_q_a[0]_PORT_A_data_out, RB1_q_a[0]_clock_0, , , );
RB1_q_a[2] = RB1_q_a[0]_PORT_A_data_out_reg[2];

--RB1_q_a[1] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[1] at M4K_X13_Y8
RB1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB1_q_a[0]_PORT_A_data_in_reg = DFFE(RB1_q_a[0]_PORT_A_data_in, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[0], SB1_ram_rom_data_reg[1], SB1_ram_rom_data_reg[2], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[5], SB1_ram_rom_data_reg[6], SB1_ram_rom_data_reg[7]);
RB1_q_a[0]_PORT_B_data_in_reg = DFFE(RB1_q_a[0]_PORT_B_data_in, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_a[0]_PORT_A_address_reg = DFFE(RB1_q_a[0]_PORT_A_address, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_a[0]_PORT_B_address_reg = DFFE(RB1_q_a[0]_PORT_B_address, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_PORT_A_write_enable = GND;
RB1_q_a[0]_PORT_A_write_enable_reg = DFFE(RB1_q_a[0]_PORT_A_write_enable, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_write_enable = SB1L2;
RB1_q_a[0]_PORT_B_write_enable_reg = DFFE(RB1_q_a[0]_PORT_B_write_enable, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_clock_0 = GLOBAL(clk);
RB1_q_a[0]_clock_1 = GLOBAL(A1L5);
RB1_q_a[0]_PORT_A_data_out = MEMORY(RB1_q_a[0]_PORT_A_data_in_reg, RB1_q_a[0]_PORT_B_data_in_reg, RB1_q_a[0]_PORT_A_address_reg, RB1_q_a[0]_PORT_B_address_reg, RB1_q_a[0]_PORT_A_write_enable_reg, RB1_q_a[0]_PORT_B_write_enable_reg, , , RB1_q_a[0]_clock_0, RB1_q_a[0]_clock_1, , , , );
RB1_q_a[0]_PORT_A_data_out_reg = DFFE(RB1_q_a[0]_PORT_A_data_out, RB1_q_a[0]_clock_0, , , );
RB1_q_a[1] = RB1_q_a[0]_PORT_A_data_out_reg[1];

--RB1_q_b[7] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[7] at M4K_X13_Y8
RB1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB1_q_b[0]_PORT_A_data_in_reg = DFFE(RB1_q_b[0]_PORT_A_data_in, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[0], SB1_ram_rom_data_reg[1], SB1_ram_rom_data_reg[2], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[5], SB1_ram_rom_data_reg[6], SB1_ram_rom_data_reg[7]);
RB1_q_b[0]_PORT_B_data_in_reg = DFFE(RB1_q_b[0]_PORT_B_data_in, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_b[0]_PORT_A_address_reg = DFFE(RB1_q_b[0]_PORT_A_address, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_b[0]_PORT_B_address_reg = DFFE(RB1_q_b[0]_PORT_B_address, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_PORT_A_write_enable = GND;
RB1_q_b[0]_PORT_A_write_enable_reg = DFFE(RB1_q_b[0]_PORT_A_write_enable, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_write_enable = SB1L2;
RB1_q_b[0]_PORT_B_write_enable_reg = DFFE(RB1_q_b[0]_PORT_B_write_enable, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_clock_0 = GLOBAL(clk);
RB1_q_b[0]_clock_1 = GLOBAL(A1L5);
RB1_q_b[0]_PORT_B_data_out = MEMORY(RB1_q_b[0]_PORT_A_data_in_reg, RB1_q_b[0]_PORT_B_data_in_reg, RB1_q_b[0]_PORT_A_address_reg, RB1_q_b[0]_PORT_B_address_reg, RB1_q_b[0]_PORT_A_write_enable_reg, RB1_q_b[0]_PORT_B_write_enable_reg, , , RB1_q_b[0]_clock_0, RB1_q_b[0]_clock_1, , , , );
RB1_q_b[7] = RB1_q_b[0]_PORT_B_data_out[7];

--RB1_q_b[6] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[6] at M4K_X13_Y8
RB1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB1_q_b[0]_PORT_A_data_in_reg = DFFE(RB1_q_b[0]_PORT_A_data_in, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[0], SB1_ram_rom_data_reg[1], SB1_ram_rom_data_reg[2], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[5], SB1_ram_rom_data_reg[6], SB1_ram_rom_data_reg[7]);
RB1_q_b[0]_PORT_B_data_in_reg = DFFE(RB1_q_b[0]_PORT_B_data_in, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_b[0]_PORT_A_address_reg = DFFE(RB1_q_b[0]_PORT_A_address, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_b[0]_PORT_B_address_reg = DFFE(RB1_q_b[0]_PORT_B_address, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_PORT_A_write_enable = GND;
RB1_q_b[0]_PORT_A_write_enable_reg = DFFE(RB1_q_b[0]_PORT_A_write_enable, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_write_enable = SB1L2;
RB1_q_b[0]_PORT_B_write_enable_reg = DFFE(RB1_q_b[0]_PORT_B_write_enable, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_clock_0 = GLOBAL(clk);
RB1_q_b[0]_clock_1 = GLOBAL(A1L5);
RB1_q_b[0]_PORT_B_data_out = MEMORY(RB1_q_b[0]_PORT_A_data_in_reg, RB1_q_b[0]_PORT_B_data_in_reg, RB1_q_b[0]_PORT_A_address_reg, RB1_q_b[0]_PORT_B_address_reg, RB1_q_b[0]_PORT_A_write_enable_reg, RB1_q_b[0]_PORT_B_write_enable_reg, , , RB1_q_b[0]_clock_0, RB1_q_b[0]_clock_1, , , , );
RB1_q_b[6] = RB1_q_b[0]_PORT_B_data_out[6];

--RB1_q_b[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[5] at M4K_X13_Y8
RB1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB1_q_b[0]_PORT_A_data_in_reg = DFFE(RB1_q_b[0]_PORT_A_data_in, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[0], SB1_ram_rom_data_reg[1], SB1_ram_rom_data_reg[2], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[5], SB1_ram_rom_data_reg[6], SB1_ram_rom_data_reg[7]);
RB1_q_b[0]_PORT_B_data_in_reg = DFFE(RB1_q_b[0]_PORT_B_data_in, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_b[0]_PORT_A_address_reg = DFFE(RB1_q_b[0]_PORT_A_address, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_b[0]_PORT_B_address_reg = DFFE(RB1_q_b[0]_PORT_B_address, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_PORT_A_write_enable = GND;
RB1_q_b[0]_PORT_A_write_enable_reg = DFFE(RB1_q_b[0]_PORT_A_write_enable, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_write_enable = SB1L2;
RB1_q_b[0]_PORT_B_write_enable_reg = DFFE(RB1_q_b[0]_PORT_B_write_enable, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_clock_0 = GLOBAL(clk);
RB1_q_b[0]_clock_1 = GLOBAL(A1L5);
RB1_q_b[0]_PORT_B_data_out = MEMORY(RB1_q_b[0]_PORT_A_data_in_reg, RB1_q_b[0]_PORT_B_data_in_reg, RB1_q_b[0]_PORT_A_address_reg, RB1_q_b[0]_PORT_B_address_reg, RB1_q_b[0]_PORT_A_write_enable_reg, RB1_q_b[0]_PORT_B_write_enable_reg, , , RB1_q_b[0]_clock_0, RB1_q_b[0]_clock_1, , , , );
RB1_q_b[5] = RB1_q_b[0]_PORT_B_data_out[5];

--RB1_q_b[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[4] at M4K_X13_Y8
RB1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB1_q_b[0]_PORT_A_data_in_reg = DFFE(RB1_q_b[0]_PORT_A_data_in, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[0], SB1_ram_rom_data_reg[1], SB1_ram_rom_data_reg[2], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[5], SB1_ram_rom_data_reg[6], SB1_ram_rom_data_reg[7]);
RB1_q_b[0]_PORT_B_data_in_reg = DFFE(RB1_q_b[0]_PORT_B_data_in, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_b[0]_PORT_A_address_reg = DFFE(RB1_q_b[0]_PORT_A_address, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_b[0]_PORT_B_address_reg = DFFE(RB1_q_b[0]_PORT_B_address, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_PORT_A_write_enable = GND;
RB1_q_b[0]_PORT_A_write_enable_reg = DFFE(RB1_q_b[0]_PORT_A_write_enable, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_write_enable = SB1L2;
RB1_q_b[0]_PORT_B_write_enable_reg = DFFE(RB1_q_b[0]_PORT_B_write_enable, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_clock_0 = GLOBAL(clk);
RB1_q_b[0]_clock_1 = GLOBAL(A1L5);
RB1_q_b[0]_PORT_B_data_out = MEMORY(RB1_q_b[0]_PORT_A_data_in_reg, RB1_q_b[0]_PORT_B_data_in_reg, RB1_q_b[0]_PORT_A_address_reg, RB1_q_b[0]_PORT_B_address_reg, RB1_q_b[0]_PORT_A_write_enable_reg, RB1_q_b[0]_PORT_B_write_enable_reg, , , RB1_q_b[0]_clock_0, RB1_q_b[0]_clock_1, , , , );
RB1_q_b[4] = RB1_q_b[0]_PORT_B_data_out[4];

--RB1_q_b[3] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[3] at M4K_X13_Y8
RB1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB1_q_b[0]_PORT_A_data_in_reg = DFFE(RB1_q_b[0]_PORT_A_data_in, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[0], SB1_ram_rom_data_reg[1], SB1_ram_rom_data_reg[2], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[5], SB1_ram_rom_data_reg[6], SB1_ram_rom_data_reg[7]);
RB1_q_b[0]_PORT_B_data_in_reg = DFFE(RB1_q_b[0]_PORT_B_data_in, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_b[0]_PORT_A_address_reg = DFFE(RB1_q_b[0]_PORT_A_address, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_b[0]_PORT_B_address_reg = DFFE(RB1_q_b[0]_PORT_B_address, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_PORT_A_write_enable = GND;
RB1_q_b[0]_PORT_A_write_enable_reg = DFFE(RB1_q_b[0]_PORT_A_write_enable, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_write_enable = SB1L2;
RB1_q_b[0]_PORT_B_write_enable_reg = DFFE(RB1_q_b[0]_PORT_B_write_enable, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_clock_0 = GLOBAL(clk);
RB1_q_b[0]_clock_1 = GLOBAL(A1L5);
RB1_q_b[0]_PORT_B_data_out = MEMORY(RB1_q_b[0]_PORT_A_data_in_reg, RB1_q_b[0]_PORT_B_data_in_reg, RB1_q_b[0]_PORT_A_address_reg, RB1_q_b[0]_PORT_B_address_reg, RB1_q_b[0]_PORT_A_write_enable_reg, RB1_q_b[0]_PORT_B_write_enable_reg, , , RB1_q_b[0]_clock_0, RB1_q_b[0]_clock_1, , , , );
RB1_q_b[3] = RB1_q_b[0]_PORT_B_data_out[3];
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