phase_shift_sin.fit.eqn

实现低频率的移相信号发生器,才用DDS技术直接的合成

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--RB1_q_a[0] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[0] at M4K_X13_Y8
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 256, Port A Width: 8, Port B Depth: 256, Port B Width: 8
--Port A Logical Depth: 256, Port A Logical Width: 8, Port B Logical Depth: 256, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
RB1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB1_q_a[0]_PORT_A_data_in_reg = DFFE(RB1_q_a[0]_PORT_A_data_in, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[0], SB1_ram_rom_data_reg[1], SB1_ram_rom_data_reg[2], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[5], SB1_ram_rom_data_reg[6], SB1_ram_rom_data_reg[7]);
RB1_q_a[0]_PORT_B_data_in_reg = DFFE(RB1_q_a[0]_PORT_B_data_in, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_a[0]_PORT_A_address_reg = DFFE(RB1_q_a[0]_PORT_A_address, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_a[0]_PORT_B_address_reg = DFFE(RB1_q_a[0]_PORT_B_address, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_PORT_A_write_enable = GND;
RB1_q_a[0]_PORT_A_write_enable_reg = DFFE(RB1_q_a[0]_PORT_A_write_enable, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_write_enable = SB1L2;
RB1_q_a[0]_PORT_B_write_enable_reg = DFFE(RB1_q_a[0]_PORT_B_write_enable, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_clock_0 = GLOBAL(clk);
RB1_q_a[0]_clock_1 = GLOBAL(A1L5);
RB1_q_a[0]_PORT_A_data_out = MEMORY(RB1_q_a[0]_PORT_A_data_in_reg, RB1_q_a[0]_PORT_B_data_in_reg, RB1_q_a[0]_PORT_A_address_reg, RB1_q_a[0]_PORT_B_address_reg, RB1_q_a[0]_PORT_A_write_enable_reg, RB1_q_a[0]_PORT_B_write_enable_reg, , , RB1_q_a[0]_clock_0, RB1_q_a[0]_clock_1, , , , );
RB1_q_a[0]_PORT_A_data_out_reg = DFFE(RB1_q_a[0]_PORT_A_data_out, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0] = RB1_q_a[0]_PORT_A_data_out_reg[0];

--RB1_q_b[0] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_b[0] at M4K_X13_Y8
RB1_q_b[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB1_q_b[0]_PORT_A_data_in_reg = DFFE(RB1_q_b[0]_PORT_A_data_in, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[0], SB1_ram_rom_data_reg[1], SB1_ram_rom_data_reg[2], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[5], SB1_ram_rom_data_reg[6], SB1_ram_rom_data_reg[7]);
RB1_q_b[0]_PORT_B_data_in_reg = DFFE(RB1_q_b[0]_PORT_B_data_in, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_b[0]_PORT_A_address_reg = DFFE(RB1_q_b[0]_PORT_A_address, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_b[0]_PORT_B_address_reg = DFFE(RB1_q_b[0]_PORT_B_address, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_PORT_A_write_enable = GND;
RB1_q_b[0]_PORT_A_write_enable_reg = DFFE(RB1_q_b[0]_PORT_A_write_enable, RB1_q_b[0]_clock_0, , , );
RB1_q_b[0]_PORT_B_write_enable = SB1L2;
RB1_q_b[0]_PORT_B_write_enable_reg = DFFE(RB1_q_b[0]_PORT_B_write_enable, RB1_q_b[0]_clock_1, , , );
RB1_q_b[0]_clock_0 = GLOBAL(clk);
RB1_q_b[0]_clock_1 = GLOBAL(A1L5);
RB1_q_b[0]_PORT_B_data_out = MEMORY(RB1_q_b[0]_PORT_A_data_in_reg, RB1_q_b[0]_PORT_B_data_in_reg, RB1_q_b[0]_PORT_A_address_reg, RB1_q_b[0]_PORT_B_address_reg, RB1_q_b[0]_PORT_A_write_enable_reg, RB1_q_b[0]_PORT_B_write_enable_reg, , , RB1_q_b[0]_clock_0, RB1_q_b[0]_clock_1, , , , );
RB1_q_b[0] = RB1_q_b[0]_PORT_B_data_out[0];

--RB1_q_a[7] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[7] at M4K_X13_Y8
RB1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB1_q_a[0]_PORT_A_data_in_reg = DFFE(RB1_q_a[0]_PORT_A_data_in, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[0], SB1_ram_rom_data_reg[1], SB1_ram_rom_data_reg[2], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[5], SB1_ram_rom_data_reg[6], SB1_ram_rom_data_reg[7]);
RB1_q_a[0]_PORT_B_data_in_reg = DFFE(RB1_q_a[0]_PORT_B_data_in, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_a[0]_PORT_A_address_reg = DFFE(RB1_q_a[0]_PORT_A_address, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_a[0]_PORT_B_address_reg = DFFE(RB1_q_a[0]_PORT_B_address, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_PORT_A_write_enable = GND;
RB1_q_a[0]_PORT_A_write_enable_reg = DFFE(RB1_q_a[0]_PORT_A_write_enable, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_write_enable = SB1L2;
RB1_q_a[0]_PORT_B_write_enable_reg = DFFE(RB1_q_a[0]_PORT_B_write_enable, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_clock_0 = GLOBAL(clk);
RB1_q_a[0]_clock_1 = GLOBAL(A1L5);
RB1_q_a[0]_PORT_A_data_out = MEMORY(RB1_q_a[0]_PORT_A_data_in_reg, RB1_q_a[0]_PORT_B_data_in_reg, RB1_q_a[0]_PORT_A_address_reg, RB1_q_a[0]_PORT_B_address_reg, RB1_q_a[0]_PORT_A_write_enable_reg, RB1_q_a[0]_PORT_B_write_enable_reg, , , RB1_q_a[0]_clock_0, RB1_q_a[0]_clock_1, , , , );
RB1_q_a[0]_PORT_A_data_out_reg = DFFE(RB1_q_a[0]_PORT_A_data_out, RB1_q_a[0]_clock_0, , , );
RB1_q_a[7] = RB1_q_a[0]_PORT_A_data_out_reg[7];

--RB1_q_a[6] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[6] at M4K_X13_Y8
RB1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB1_q_a[0]_PORT_A_data_in_reg = DFFE(RB1_q_a[0]_PORT_A_data_in, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[0], SB1_ram_rom_data_reg[1], SB1_ram_rom_data_reg[2], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[5], SB1_ram_rom_data_reg[6], SB1_ram_rom_data_reg[7]);
RB1_q_a[0]_PORT_B_data_in_reg = DFFE(RB1_q_a[0]_PORT_B_data_in, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_a[0]_PORT_A_address_reg = DFFE(RB1_q_a[0]_PORT_A_address, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_a[0]_PORT_B_address_reg = DFFE(RB1_q_a[0]_PORT_B_address, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_PORT_A_write_enable = GND;
RB1_q_a[0]_PORT_A_write_enable_reg = DFFE(RB1_q_a[0]_PORT_A_write_enable, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_write_enable = SB1L2;
RB1_q_a[0]_PORT_B_write_enable_reg = DFFE(RB1_q_a[0]_PORT_B_write_enable, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_clock_0 = GLOBAL(clk);
RB1_q_a[0]_clock_1 = GLOBAL(A1L5);
RB1_q_a[0]_PORT_A_data_out = MEMORY(RB1_q_a[0]_PORT_A_data_in_reg, RB1_q_a[0]_PORT_B_data_in_reg, RB1_q_a[0]_PORT_A_address_reg, RB1_q_a[0]_PORT_B_address_reg, RB1_q_a[0]_PORT_A_write_enable_reg, RB1_q_a[0]_PORT_B_write_enable_reg, , , RB1_q_a[0]_clock_0, RB1_q_a[0]_clock_1, , , , );
RB1_q_a[0]_PORT_A_data_out_reg = DFFE(RB1_q_a[0]_PORT_A_data_out, RB1_q_a[0]_clock_0, , , );
RB1_q_a[6] = RB1_q_a[0]_PORT_A_data_out_reg[6];

--RB1_q_a[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[5] at M4K_X13_Y8
RB1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB1_q_a[0]_PORT_A_data_in_reg = DFFE(RB1_q_a[0]_PORT_A_data_in, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[0], SB1_ram_rom_data_reg[1], SB1_ram_rom_data_reg[2], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[5], SB1_ram_rom_data_reg[6], SB1_ram_rom_data_reg[7]);
RB1_q_a[0]_PORT_B_data_in_reg = DFFE(RB1_q_a[0]_PORT_B_data_in, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_a[0]_PORT_A_address_reg = DFFE(RB1_q_a[0]_PORT_A_address, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_a[0]_PORT_B_address_reg = DFFE(RB1_q_a[0]_PORT_B_address, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_PORT_A_write_enable = GND;
RB1_q_a[0]_PORT_A_write_enable_reg = DFFE(RB1_q_a[0]_PORT_A_write_enable, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_write_enable = SB1L2;
RB1_q_a[0]_PORT_B_write_enable_reg = DFFE(RB1_q_a[0]_PORT_B_write_enable, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_clock_0 = GLOBAL(clk);
RB1_q_a[0]_clock_1 = GLOBAL(A1L5);
RB1_q_a[0]_PORT_A_data_out = MEMORY(RB1_q_a[0]_PORT_A_data_in_reg, RB1_q_a[0]_PORT_B_data_in_reg, RB1_q_a[0]_PORT_A_address_reg, RB1_q_a[0]_PORT_B_address_reg, RB1_q_a[0]_PORT_A_write_enable_reg, RB1_q_a[0]_PORT_B_write_enable_reg, , , RB1_q_a[0]_clock_0, RB1_q_a[0]_clock_1, , , , );
RB1_q_a[0]_PORT_A_data_out_reg = DFFE(RB1_q_a[0]_PORT_A_data_out, RB1_q_a[0]_clock_0, , , );
RB1_q_a[5] = RB1_q_a[0]_PORT_A_data_out_reg[5];

--RB1_q_a[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[4] at M4K_X13_Y8
RB1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB1_q_a[0]_PORT_A_data_in_reg = DFFE(RB1_q_a[0]_PORT_A_data_in, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[0], SB1_ram_rom_data_reg[1], SB1_ram_rom_data_reg[2], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[5], SB1_ram_rom_data_reg[6], SB1_ram_rom_data_reg[7]);
RB1_q_a[0]_PORT_B_data_in_reg = DFFE(RB1_q_a[0]_PORT_B_data_in, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_a[0]_PORT_A_address_reg = DFFE(RB1_q_a[0]_PORT_A_address, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);
RB1_q_a[0]_PORT_B_address_reg = DFFE(RB1_q_a[0]_PORT_B_address, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_PORT_A_write_enable = GND;
RB1_q_a[0]_PORT_A_write_enable_reg = DFFE(RB1_q_a[0]_PORT_A_write_enable, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_write_enable = SB1L2;
RB1_q_a[0]_PORT_B_write_enable_reg = DFFE(RB1_q_a[0]_PORT_B_write_enable, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_clock_0 = GLOBAL(clk);
RB1_q_a[0]_clock_1 = GLOBAL(A1L5);
RB1_q_a[0]_PORT_A_data_out = MEMORY(RB1_q_a[0]_PORT_A_data_in_reg, RB1_q_a[0]_PORT_B_data_in_reg, RB1_q_a[0]_PORT_A_address_reg, RB1_q_a[0]_PORT_B_address_reg, RB1_q_a[0]_PORT_A_write_enable_reg, RB1_q_a[0]_PORT_B_write_enable_reg, , , RB1_q_a[0]_clock_0, RB1_q_a[0]_clock_1, , , , );
RB1_q_a[0]_PORT_A_data_out_reg = DFFE(RB1_q_a[0]_PORT_A_data_out, RB1_q_a[0]_clock_0, , , );
RB1_q_a[4] = RB1_q_a[0]_PORT_A_data_out_reg[4];

--RB1_q_a[3] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[3] at M4K_X13_Y8
RB1_q_a[0]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
RB1_q_a[0]_PORT_A_data_in_reg = DFFE(RB1_q_a[0]_PORT_A_data_in, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_data_in = BUS(SB1_ram_rom_data_reg[0], SB1_ram_rom_data_reg[1], SB1_ram_rom_data_reg[2], SB1_ram_rom_data_reg[3], SB1_ram_rom_data_reg[4], SB1_ram_rom_data_reg[5], SB1_ram_rom_data_reg[6], SB1_ram_rom_data_reg[7]);
RB1_q_a[0]_PORT_B_data_in_reg = DFFE(RB1_q_a[0]_PORT_B_data_in, RB1_q_a[0]_clock_1, , , );
RB1_q_a[0]_PORT_A_address = BUS(fword2[24], fword2[25], fword2[26], fword2[27], fword2[28], fword2[29], fword2[30], fword2[31]);
RB1_q_a[0]_PORT_A_address_reg = DFFE(RB1_q_a[0]_PORT_A_address, RB1_q_a[0]_clock_0, , , );
RB1_q_a[0]_PORT_B_address = BUS(SB1_ram_rom_addr_reg[0], SB1_ram_rom_addr_reg[1], SB1_ram_rom_addr_reg[2], SB1_ram_rom_addr_reg[3], SB1_ram_rom_addr_reg[4], SB1_ram_rom_addr_reg[5], SB1_ram_rom_addr_reg[6], SB1_ram_rom_addr_reg[7]);