phase_shift_sin.tan.summary

实现低频率的移相信号发生器,才用DDS技术直接的合成

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 2.565 ns
From           : fword[1]
To             : fword2[31]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.840 ns
From           : sin_rom:u3|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[5]
To             : fout[5]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.296 ns
From           : altera_internal_jtag
To             : sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.431 ns
From           : sin_rom:u4|altsyncram:altsyncram_component|altsyncram_66u:auto_generated|altsyncram_4r92:altsyncram1|q_a[6]
To             : pout[6]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 78.95 MHz ( period = 12.666 ns )
From           : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 147.56 MHz ( period = 6.777 ns )
From           : sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[1]
To             : sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_afd:auto_generated|safe_q[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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