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📄 phase_shift_sin.fit.talkback.xml

📁 实现低频率的移相信号发生器,才用DDS技术直接的合成
💻 XML
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	<row>
		<name>fout[3]</name>
		<pin__>68</pin__>
		<i_o_bank>4</i_o_bank>
		<x_coordinate>22</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>fout[4]</name>
		<pin__>69</pin__>
		<i_o_bank>4</i_o_bank>
		<x_coordinate>24</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>fout[5]</name>
		<pin__>70</pin__>
		<i_o_bank>4</i_o_bank>
		<x_coordinate>24</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>fout[6]</name>
		<pin__>71</pin__>
		<i_o_bank>4</i_o_bank>
		<x_coordinate>26</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>fout[7]</name>
		<pin__>72</pin__>
		<i_o_bank>4</i_o_bank>
		<x_coordinate>26</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>User</location_assigned_by>
	</row>
	<row>
		<name>pout[0]</name>
		<pin__>127</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>12</x_coordinate>
		<y_coordinate>14</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>pout[1]</name>
		<pin__>79</pin__>
		<i_o_bank>3</i_o_bank>
		<x_coordinate>27</x_coordinate>
		<y_coordinate>4</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>pout[2]</name>
		<pin__>132</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>8</x_coordinate>
		<y_coordinate>14</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>pout[3]</name>
		<pin__>128</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>12</x_coordinate>
		<y_coordinate>14</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>pout[4]</name>
		<pin__>50</pin__>
		<i_o_bank>4</i_o_bank>
		<x_coordinate>10</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>1</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>pout[5]</name>
		<pin__>124</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>16</x_coordinate>
		<y_coordinate>14</y_coordinate>
		<cell_number>0</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>pout[6]</name>
		<pin__>126</pin__>
		<i_o_bank>2</i_o_bank>
		<x_coordinate>16</x_coordinate>
		<y_coordinate>14</y_coordinate>
		<cell_number>2</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
	<row>
		<name>pout[7]</name>
		<pin__>55</pin__>
		<i_o_bank>4</i_o_bank>
		<x_coordinate>16</x_coordinate>
		<y_coordinate>0</y_coordinate>
		<cell_number>2</cell_number>
		<output_register>no</output_register>
		<output_enable_register>no</output_enable_register>
		<power_up_high>no</power_up_high>
		<slow_slew_rate>no</slow_slew_rate>
		<pci_i_o_enabled>no</pci_i_o_enabled>
		<open_drain>no</open_drain>
		<bus_hold>no</bus_hold>
		<weak_pull_up>Off</weak_pull_up>
		<i_o_standard>LVTTL</i_o_standard>
		<current_strength>24mA</current_strength>
		<termination>Off</termination>
		<location_assigned_by>Fitter</location_assigned_by>
	</row>
</output_pins>
<compilation_summary>
	<flow_status>Successful - Wed Jul 20 15:42:51 2005</flow_status>
	<quartus_ii_version>4.1 Build 181 06/29/2004 SJ Full Version</quartus_ii_version>
	<revision_name>phase_shift_sin</revision_name>
	<top_level_entity_name>phase_shift_sin</top_level_entity_name>
	<family>Cyclone</family>
	<device>EP1C3T144C8</device>
	<timing_models>Production</timing_models>
	<total_logic_elements>525 / 2,910 ( 18 % )</total_logic_elements>
	<total_pins>33 / 104 ( 31 % )</total_pins>
	<total_memory_bits>8,192 / 59,904 ( 13 % )</total_memory_bits>
	<total_plls>0 / 1 ( 0 % )</total_plls>
</compilation_summary>
<compile_id>EFA230B6</compile_id>
<files>
	<top>F:/phase_shift_sin/fpga/phase_shift_sin.vhd</top>
	<extensions>
		<ext ext_name="stp">1</ext>
		<ext ext_name="vhd">12</ext>
		<ext ext_name="vwf">1</ext>
		<ext ext_name="tdf">23</ext>
		<ext ext_name="inc">30</ext>
		<ext ext_name="lst">1</ext>
		<ext ext_name="mif">1</ext>
	</extensions>
	<sub_files>
		<sub_file>stp1.stp</sub_file>
		<sub_file>sin_rom.vhd</sub_file>
		<sub_file>adder8.vhd</sub_file>
		<sub_file>adder32.vhd</sub_file>
		<sub_file>phase_shift_sin.vhd</sub_file>
		<sub_file>phase_shift_sin.vwf</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/lpm_add_sub.tdf</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/addcore.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/look_add.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/bypassff.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/altshift.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/alt_stratix_add_sub.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/alt_mercury_add_sub.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/aglobal41.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/cbx.lst</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/addcore.tdf</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/a_csnbuffer.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/a_csnbuffer.tdf</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/altshift.tdf</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/altsyncram.tdf</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/stratix_ram_block.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/lpm_mux.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/lpm_decode.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/altsyncram.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/a_rdenreg.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/altrom.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/altram.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/altdpram.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/altqpram.inc</sub_file>
		<sub_file>F:/phase_shift_sin/fpga/db/altsyncram_a4s.tdf</sub_file>
		<sub_file>F:/phase_shift_sin/fpga/db/altsyncram_4r92.tdf</sub_file>
		<sub_file>./sinlut.mif</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/sld_rom_sr.vhd</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/sld_signaltap.vhd</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/sld_ela_control.vhd</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/lpm_shiftreg.tdf</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/lpm_constant.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/dffeea.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/sld_mbpmg.vhd</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/lpm_counter.tdf</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/lpm_add_sub.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/cmpconst.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/lpm_compare.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/lpm_counter.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/alt_synch_counter.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/alt_synch_counter_f.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/alt_counter_f10ke.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/alt_counter_stratix.inc</sub_file>
		<sub_file>F:/phase_shift_sin/fpga/db/cntr_cn8.tdf</sub_file>
		<sub_file>F:/phase_shift_sin/fpga/db/cntr_419.tdf</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/lpm_compare.tdf</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/comptree.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/comptree.tdf</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/cmpchain.inc</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/cmpchain.tdf</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/sld_acquisition_buffer.vhd</sub_file>
		<sub_file>F:/phase_shift_sin/fpga/db/cntr_1r9.tdf</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/lpm_ff.tdf</sub_file>
		<sub_file>F:/phase_shift_sin/fpga/db/altsyncram_cg82.tdf</sub_file>
		<sub_file>F:/phase_shift_sin/fpga/db/cntr_cv7.tdf</sub_file>
		<sub_file>F:/phase_shift_sin/fpga/db/cntr_nk7.tdf</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/sld_hub.vhd</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/lpm_decode.tdf</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/declut.inc</sub_file>
		<sub_file>F:/phase_shift_sin/fpga/db/decode_9ie.tdf</sub_file>
		<sub_file>d:/quartus41/libraries/megafunctions/sld_dffex.vhd</sub_file>
		<sub_file>F:/phase_shift_sin/fpga/db/cntr_v98.tdf</sub_file>
		<sub_file>F:/phase_shift_sin/fpga/db/cntr_pd8.tdf</sub_file>
	</sub_files>
</files>
<architecture>
	<family>Cyclone</family>
	<auto_device>OFF</auto_device>
	<device>EP1C3T144C8</device>
</architecture>
<pkg_io>
	<pin_std count="39">LVTTL</pin_std>
</pkg_io>
<research>
	<le_sclr>15</le_sclr>
	<le_aclr>407</le_aclr>
	<le_aload>0</le_aload>
	<le_sload>162</le_sload>
	<le_inverta>0</le_inverta>
	<le_carry_in>34</le_carry_in>
	<le_ce>159</le_ce>
	<le_clk>407</le_clk>
	<le_ce_sload>59</le_ce_sload>
	<pin_sclr>0</pin_sclr>
	<pin_aclr>0</pin_aclr>
	<pin_ce_in>0</pin_ce_in>
	<pin_ce_out>0</pin_ce_out>
</research>
</talkback>

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