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📄 phase_shift_sin.fit.talkback.xml

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<!-- 
This XML file (created on Wed Jul 20 15:42:51 2005) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>4.1</ver>
<schema>quartus_version_4.1_build_181.xsd</schema>
<license>
	<host_id>00e04cfe19e2</host_id>
	<nic_id>00e04cfe19e2</nic_id>
	<cdrive_id>a8e2db7b</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>4.1</version>
	<build>Build 181</build>
	<module>quartus_fit.exe</module>
	<edition>Full Version</edition>
	<compilation_end_time>Wed Jul 20 15:42:51 2005</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">2411</cpu_freq>
	</cpu>
	<ram units="MB">256</ram>
</machine>
<top_file>F:/phase_shift_sin/fpga/phase_shift_sin</top_file>
<resource_usage_summary>
	<rsc name="Logic cells" util="18" max=" 2910 " type="int">525 </rsc>
	<rsc name="Registers" util="12" max=" 3210 " type="int">407 </rsc>
	<rsc name="Total LABs" util="32" max=" 291 " type="int">94 </rsc>
	<rsc name="Logic elements in carry chains" type="int">84</rsc>
	<rsc name="User inserted logic cells" type="int">0</rsc>
	<rsc name="Virtual pins" type="int">0</rsc>
	<rsc name="I/O pins" util="31" max=" 104 " type="int">33 </rsc>
	<rsc name="-- Clock pins" util="0" max=" 2 " type="int">0 </rsc>
	<rsc name="Global signals" type="int">8</rsc>
	<rsc name="M4Ks" util="23" max=" 13 " type="int">3 </rsc>
	<rsc name="Total memory bits" util="13" max=" 59904 " type="int">8192 </rsc>
	<rsc name="Total RAM block bits" util="23" max=" 59904 " type="int">13824 </rsc>
	<rsc name="Global clocks" util="100" max=" 8 " type="int">8 </rsc>
	<rsc name="Maximum fan-out node" type="text">altera_internal_jtag~TDO</rsc>
	<rsc name="Maximum fan-out" type="int">262</rsc>
	<rsc name="Total fan-out" type="int">2317</rsc>
	<rsc name="Average fan-out" type="float">4.08</rsc>
</resource_usage_summary>
<control_signals>
	<row>
		<name>altera_internal_jtag~TCKUTAP</name>
		<location>JTAG_X1_Y6_N1</location>
		<fan_out>255</fan_out>
		<usage>Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK2</global_line_name>
	</row>
	<row>
		<name>sld_hub:sld_hub_inst|CLEAR_SIGNAL~0</name>
		<location>LC_X19_Y6_N5</location>
		<fan_out>52</fan_out>
		<usage>Async. clear</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK0</global_line_name>
	</row>
	<row>
		<name>sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0]</name>
		<location>LC_X16_Y10_N4</location>
		<fan_out>14</fan_out>
		<usage>Async. clear</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK1</global_line_name>
	</row>
	<row>
		<name>sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[0]</name>
		<location>LC_X17_Y7_N4</location>
		<fan_out>14</fan_out>
		<usage>Async. clear</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK3</global_line_name>
	</row>
	<row>
		<name>sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]</name>
		<location>LC_X19_Y8_N6</location>
		<fan_out>15</fan_out>
		<usage>Async. clear</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK6</global_line_name>
	</row>
	<row>
		<name>sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|clear_signal</name>
		<location>LC_X18_Y8_N8</location>
		<fan_out>34</fan_out>
		<usage>Async. clear</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK5</global_line_name>
	</row>
	<row>
		<name>sld_signaltap:auto_signaltap_0|reset_all</name>
		<location>LC_X19_Y6_N4</location>
		<fan_out>104</fan_out>
		<usage>Async. clear</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK4</global_line_name>
	</row>
	<row>
		<name>clk</name>
		<location>PIN_123</location>
		<fan_out>158</fan_out>
		<usage>Clock</usage>
		<global>yes</global>
		<global_resource_used>Global clock</global_resource_used>
		<global_line_name>GCLK7</global_line_name>
	</row>
</control_signals>
<non_global_high_fan_out_signals>
	<row>
		<name>sin_rom:u3|altsyncram:altsyncram_component|altsyncram_a4s:auto_generated|altsyncram_4r92:altsyncram1|q_a[7]</name>
		<fan_out>2</fan_out>
	</row>
	<row>
		<name>sin_rom:u3|altsyncram:altsyncram_component|altsyncram_a4s:auto_generated|altsyncram_4r92:altsyncram1|q_b[7]</name>
		<fan_out>1</fan_out>
	</row>
	<row>
		<name>sin_rom:u3|altsyncram:altsyncram_component|altsyncram_a4s:auto_generated|altsyncram_4r92:altsyncram1|q_a[0]</name>
		<fan_out>2</fan_out>
	</row>
	<row>
		<name>sin_rom:u3|altsyncram:altsyncram_component|altsyncram_a4s:auto_generated|altsyncram_4r92:altsyncram1|q_a[1]</name>
		<fan_out>2</fan_out>
	</row>
	<row>
		<name>sin_rom:u3|altsyncram:altsyncram_component|altsyncram_a4s:auto_generated|altsyncram_4r92:altsyncram1|q_a[2]</name>
		<fan_out>2</fan_out>
	</row>
	<row>
		<name>sin_rom:u3|altsyncram:altsyncram_component|altsyncram_a4s:auto_generated|altsyncram_4r92:altsyncram1|q_a[3]</name>
		<fan_out>2</fan_out>
	</row>
	<row>
		<name>sin_rom:u3|altsyncram:altsyncram_component|altsyncram_a4s:auto_generated|altsyncram_4r92:altsyncram1|q_a[4]</name>
		<fan_out>2</fan_out>
	</row>
	<row>
		<name>sin_rom:u3|altsyncram:altsyncram_component|altsyncram_a4s:auto_generated|altsyncram_4r92:altsyncram1|q_a[5]</name>
		<fan_out>2</fan_out>
	</row>
	<row>
		<name>sin_rom:u3|altsyncram:altsyncram_component|altsyncram_a4s:auto_generated|altsyncram_4r92:altsyncram1|q_a[6]</name>
		<fan_out>2</fan_out>
	</row>
	<row>
		<name>sin_rom:u3|altsyncram:altsyncram_component|altsyncram_a4s:auto_generated|altsyncram_4r92:altsyncram1|q_b[0]</name>
		<fan_out>1</fan_out>
	</row>
</non_global_high_fan_out_signals>
<ram_summary>
	<row>
		<name>sin_rom:u3|altsyncram:altsyncram_component|altsyncram_a4s:auto_generated|altsyncram_4r92:altsyncram1|ALTSYNCRAM</name>
		<type>AUTO</type>
		<mode>True Dual Port</mode>
		<port_a_depth>256</port_a_depth>
		<port_a_width>8</port_a_width>
		<port_b_depth>256</port_b_depth>
		<port_b_width>8</port_b_width>
		<size>2048</size>
		<m4ks>1</m4ks>
		<mif>.\sinlut.mif</mif>
		<location>M4K_X13_Y8</location>
	</row>
	<row>
		<name>sin_rom:u4|altsyncram:altsyncram_component|altsyncram_a4s:auto_generated|altsyncram_4r92:altsyncram1|ALTSYNCRAM</name>
		<type>AUTO</type>
		<mode>True Dual Port</mode>
		<port_a_depth>256</port_a_depth>
		<port_a_width>8</port_a_width>
		<port_b_depth>256</port_b_depth>
		<port_b_width>8</port_b_width>
		<size>2048</size>
		<m4ks>1</m4ks>
		<mif>.\sinlut.mif</mif>
		<location>M4K_X13_Y6</location>
	</row>
	<row>
		<name>sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_cg82:auto_generated|ALTSYNCRAM</name>
		<type>M4K</type>
		<mode>Simple Dual Port</mode>
		<port_a_depth>128</port_a_depth>
		<port_a_width>32</port_a_width>
		<port_b_depth>128</port_b_depth>
		<port_b_width>32</port_b_width>
		<size>4096</size>
		<m4ks>1</m4ks>
		<mif>None</mif>
		<location>M4K_X13_Y5</location>
	</row>
</ram_summary>
<interconnect_usage_summary>
	<rsc name="M4K buffers" util="13" max=" 468 " type="int">64 </rsc>
	<rsc name="Local interconnects" util="6" max=" 11506 " type="int">759 </rsc>
	<rsc name="LUT chains" util="1" max=" 2619 " type="int">18 </rsc>
	<rsc name="R4s" util="5" max=" 7520 " type="int">438 </rsc>
	<rsc name="C4s" util="4" max=" 8840 " type="int">404 </rsc>
	<rsc name="Global clocks" util="100" max=" 8 " type="int">8 </rsc>
	<rsc name="LAB clocks" util="32" max=" 156 " type="int">50 </rsc>
	<rsc name="Direct links" util="1" max=" 11506 " type="int">93 </rsc>
</interconnect_usage_summary>
<mep_data>
	<command_line>quartus_fit --import_settings_files=off --export_settings_files=off phase_shift_sin -c phase_shift_sin</command_line>
</mep_data>
<software_data>
	<speed_disk_usage_tradeoff>normal</speed_disk_usage_tradeoff>
</software_data>
<fitter_settings>
	<row>
		<option>Device</option>
		<setting>EP1C3T144C8</setting>
	</row>
	<row>
		<option>Optimize Hold Timing</option>
		<setting>IO Paths and Minimum TPD Paths</setting>
		<default_value>IO Paths and Minimum TPD Paths</default_value>
	</row>
	<row>
		<option>Optimize Timing</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>Optimize IOC Register Placement for Timing</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit to One Fitting Attempt</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Final Placement Optimizations</option>
		<setting>Automatically</setting>
		<default_value>Automatically</default_value>
	</row>
	<row>
		<option>Fitter Initial Placement Seed</option>
		<setting>1</setting>
		<default_value>1</default_value>
	</row>
	<row>
		<option>Slow Slew Rate</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>PCI I/O</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Weak Pull-Up Resistor</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Enable Bus-Hold Circuitry</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Global Memory Control Signals</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Packed Registers -- Cyclone</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Auto Delay Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Merge PLLs</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Perform Physical Synthesis for Combinational Logic</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Perform Register Duplication</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Perform Register Retiming</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Physical Synthesis Effort Level</option>
		<setting>Normal</setting>
		<default_value>Normal</default_value>
	</row>
	<row>
		<option>Logic Cell Insertion -- Logic Duplication</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Auto Register Duplication</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Global Clock</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Global Register Control Signals</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
</fitter_settings>
<fitter_device_options>
	<row>
		<option>Auto-restart configuration after error</option>
		<setting>On</setting>
	</row>
	<row>
		<option>Release clears before tri-states</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable user-supplied start-up clock (CLKUSR)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide reset (DEV_CLRn)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable device-wide output enable (DEV_OE)</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Enable INIT_DONE output</option>
		<setting>Off</setting>
	</row>
	<row>
		<option>Configuration scheme</option>
		<setting>Active Serial</setting>
	</row>
	<row>
		<option>Reserve all unused pins</option>
		<setting>As output driving ground</setting>
	</row>
	<row>
		<option>Base pin-out file on sameframe device</option>
		<setting>Off</setting>
	</row>
</fitter_device_options>
<input_pins>
	<row>
		<name>clk</name>
123

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