📄 phase_shift_sin.map.talkback.xml
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<!--
This XML file (created on Wed Jul 20 15:42:30 2005) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature. To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder. For more information, go
to license.txt.
-->
<talkback>
<ver>4.1</ver>
<schema>quartus_version_4.1_build_181.xsd</schema>
<license>
<host_id>00e04cfe19e2</host_id>
<nic_id>00e04cfe19e2</nic_id>
<cdrive_id>a8e2db7b</cdrive_id>
</license>
<tool>
<name>Quartus II</name>
<version>4.1</version>
<build>Build 181</build>
<module>quartus_map.exe</module>
<edition>Full Version</edition>
<compilation_end_time>Wed Jul 20 15:42:30 2005</compilation_end_time>
</tool>
<machine>
<os>Windows XP</os>
<cpu>
<proc_count>1</proc_count>
<cpu_freq units="MHz">2411</cpu_freq>
</cpu>
<ram units="MB">256</ram>
</machine>
<top_file>F:/phase_shift_sin/fpga/phase_shift_sin</top_file>
<mep_data>
<command_line>quartus_map --import_settings_files=on --export_settings_files=off phase_shift_sin -c phase_shift_sin</command_line>
</mep_data>
<software_data>
<speed_disk_usage_tradeoff>normal</speed_disk_usage_tradeoff>
</software_data>
<analysis___synthesis_settings>
<row>
<option>Device</option>
<setting>EP1C3T144C8</setting>
</row>
<row>
<option>Family name</option>
<setting>Cyclone</setting>
<default_value>Stratix</default_value>
</row>
<row>
<option>Restructure Multiplexers</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Create Debugging Nodes for IP Cores</option>
<setting>off</setting>
<default_value>off</default_value>
</row>
<row>
<option>Disk space/compilation speed tradeoff</option>
<setting>Normal</setting>
<default_value>Normal</default_value>
</row>
<row>
<option>Preserve fewer node names</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Disable OpenCore Plus hardware evaluation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Verilog Version</option>
<setting>Verilog_2001</setting>
<default_value>Verilog_2001</default_value>
</row>
<row>
<option>VHDL Version</option>
<setting>VHDL93</setting>
<default_value>VHDL93</default_value>
</row>
<row>
<option>Top-level entity name</option>
<setting>phase_shift_sin</setting>
<default_value>phase_shift_sin</default_value>
</row>
<row>
<option>State Machine Processing</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>NOT Gate Push-Back</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Power-Up Don't Care</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Remove Redundant Logic Cells</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Remove Duplicate Registers</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Ignore CARRY Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore CASCADE Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore GLOBAL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore ROW GLOBAL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore LCELL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore SOFT Buffers</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Limit AHDL Integers to 32 Bits</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Optimization Technique -- Cyclone</option>
<setting>Balanced</setting>
<default_value>Balanced</default_value>
</row>
<row>
<option>Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II</option>
<setting>70</setting>
<default_value>70</default_value>
</row>
<row>
<option>Auto Carry Chains</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Open-Drain Pins</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Remove Duplicate Logic</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Perform WYSIWYG Primitive Resynthesis</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Perform gate-level register retiming</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Allow register retiming to trade off Tsu/Tco with Fmax</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto ROM Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto RAM Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Shift Register Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Clock Enable Replacement</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Allows Synchronous Control Signal Usage in Normal Mode Logic Cells</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Resource Sharing</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Allow Any RAM Size For Recognition</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Allow Any ROM Size For Recognition</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Allow Any Shift Register Size For Recognition</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
</analysis___synthesis_settings>
<general_register_statistics>
<row>
<statistic>Number of registers using Synchronous Clear</statistic>
<value>15</value>
</row>
<row>
<statistic>Number of registers using Synchronous Load</statistic>
<value>33</value>
</row>
<row>
<statistic>Number of registers using Asynchronous Clear</statistic>
<value>250</value>
</row>
<row>
<statistic>Number of registers using Asynchronous Load</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Clock Enable</statistic>
<value>159</value>
</row>
<row>
<statistic>Number of registers using Output Enable</statistic>
<value>0</value>
</row>
<row>
<statistic>Number of registers using Preset</statistic>
<value>0</value>
</row>
</general_register_statistics>
<signaltap_ii_logic_analyzer_settings>
<row>
<instance_index>0</instance_index>
<instance_name>auto_signaltap_0</instance_name>
<trigger_input_width>1</trigger_input_width>
<data_input_width>32</data_input_width>
<sample_depth>128</sample_depth>
<trigger_levels>1</trigger_levels>
<advanced_trigger_levels>0</advanced_trigger_levels>
<trigger_in_used>no</trigger_in_used>
<trigger_out_used>no</trigger_out_used>
<incremental_trigger_inputs>1</incremental_trigger_inputs>
<incremental_data_inputs>0</incremental_data_inputs>
</row>
</signaltap_ii_logic_analyzer_settings>
<in_system_memory_content_editor_setting>
<row>
<instance_index>0</instance_index>
<instance_id>NONE</instance_id>
<width>8</width>
<depth>256</depth>
<mode>Read/Write</mode>
<hierarchy_location>|phase_shift_sin|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_a4s:auto_generated</hierarchy_location>
</row>
<row>
<instance_index>1</instance_index>
<instance_id>NONE</instance_id>
<width>8</width>
<depth>256</depth>
<mode>Read/Write</mode>
<hierarchy_location>|phase_shift_sin|sin_rom:u4|altsyncram:altsyncram_component|altsyncram_a4s:auto_generated</hierarchy_location>
</row>
</in_system_memory_content_editor_setting>
<ip_cores>
<ip type="ampp">
<corename>sld_mod_ram_rom.vhd</corename>
<vendor_id>6AF7</vendor_id>
<product_id>BCEC</product_id>
<pof>on</pof>
<to>on</to>
<edo_vho_vo>on</edo_vho_vo>
<source_view>off</source_view>
</ip>
<ip type="ampp">
<corename>sld_rom_sr.vhd</corename>
<vendor_id>6AF7</vendor_id>
<product_id>BCE1</product_id>
<pof>on</pof>
<to>on</to>
<edo_vho_vo>on</edo_vho_vo>
<source_view>off</source_view>
</ip>
<ip type="ampp">
<corename>sld_signaltap.vhd</corename>
<vendor_id>6AF7</vendor_id>
<product_id>BCEC</product_id>
<pof>on</pof>
<to>on</to>
<edo_vho_vo>on</edo_vho_vo>
<source_view>off</source_view>
</ip>
<ip type="ampp">
<corename>sld_ela_control.vhd</corename>
<vendor_id>6AF7</vendor_id>
<product_id>BCEC</product_id>
<pof>on</pof>
<to>on</to>
<edo_vho_vo>on</edo_vho_vo>
<source_view>off</source_view>
</ip>
<ip type="ampp">
<corename>sld_mbpmg.vhd</corename>
<vendor_id>6AF7</vendor_id>
<product_id>BCEC</product_id>
<pof>on</pof>
<to>on</to>
<edo_vho_vo>on</edo_vho_vo>
<source_view>off</source_view>
</ip>
<ip type="ampp">
<corename>sld_acquisition_buffer.vhd</corename>
<vendor_id>6AF7</vendor_id>
<product_id>BCEC</product_id>
<pof>on</pof>
<to>on</to>
<edo_vho_vo>on</edo_vho_vo>
<source_view>off</source_view>
</ip>
<ip type="ampp">
<corename>sld_hub.vhd</corename>
<vendor_id>6AF7</vendor_id>
<product_id>BCE1</product_id>
<pof>on</pof>
<to>on</to>
<edo_vho_vo>on</edo_vho_vo>
<source_view>off</source_view>
</ip>
<ip type="ampp">
<corename>sld_dffex.vhd</corename>
<vendor_id>6AF7</vendor_id>
<product_id>BCE1</product_id>
<pof>on</pof>
<to>on</to>
<edo_vho_vo>on</edo_vho_vo>
<source_view>off</source_view>
</ip>
</ip_cores>
<compilation_summary>
<flow_status>Successful - Wed Jul 20 15:42:29 2005</flow_status>
<quartus_ii_version>4.1 Build 181 06/29/2004 SJ Full Version</quartus_ii_version>
<revision_name>phase_shift_sin</revision_name>
<top_level_entity_name>phase_shift_sin</top_level_entity_name>
<family>Cyclone</family>
<device>EP1C3T144C8</device>
<timing_models>Production</timing_models>
<total_logic_elements>562</total_logic_elements>
<total_pins>37</total_pins>
<total_memory_bits>8,192</total_memory_bits>
<total_plls>0</total_plls>
</compilation_summary>
<compile_id>1F386B16</compile_id>
</talkback>
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