fengpin.map.rpt

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; Resource                                    ; Usage         ;
+---------------------------------------------+---------------+
; Total logic elements                        ; 25            ;
;     -- Combinational with no register       ; 5             ;
;     -- Register only                        ; 0             ;
;     -- Combinational with a register        ; 20            ;
;                                             ;               ;
; Logic element usage by number of LUT inputs ;               ;
;     -- 4 input functions                    ; 5             ;
;     -- 3 input functions                    ; 10            ;
;     -- 2 input functions                    ; 5             ;
;     -- 1 input functions                    ; 5             ;
;     -- 0 input functions                    ; 0             ;
;         -- Combinational cells for routing  ; 0             ;
;                                             ;               ;
; Logic elements by mode                      ;               ;
;     -- normal mode                          ; 25            ;
;     -- arithmetic mode                      ; 0             ;
;     -- qfbk mode                            ; 0             ;
;     -- register cascade mode                ; 0             ;
;     -- synchronous clear/load mode          ; 0             ;
;     -- asynchronous clear/load mode         ; 0             ;
;                                             ;               ;
; Total registers                             ; 20            ;
; I/O pins                                    ; 2             ;
; Maximum fan-out node                        ; 74160:inst4|6 ;
; Maximum fan-out                             ; 5             ;
; Total fan-out                               ; 86            ;
; Average fan-out                             ; 3.19          ;
+---------------------------------------------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                            ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name  ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+
; |fengpin                   ; 25 (0)      ; 20           ; 0           ; 0    ; 2    ; 0            ; 5 (0)        ; 0 (0)             ; 20 (0)           ; 0 (0)           ; 0 (0)      ; |fengpin             ;
;    |74160:inst1|           ; 5 (5)       ; 4            ; 0           ; 0    ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |fengpin|74160:inst1 ;
;    |74160:inst2|           ; 5 (5)       ; 4            ; 0           ; 0    ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |fengpin|74160:inst2 ;
;    |74160:inst3|           ; 5 (5)       ; 4            ; 0           ; 0    ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |fengpin|74160:inst3 ;
;    |74160:inst4|           ; 5 (5)       ; 4            ; 0           ; 0    ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |fengpin|74160:inst4 ;
;    |74160:inst|            ; 5 (5)       ; 4            ; 0           ; 0    ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |fengpin|74160:inst  ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 20    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Jan 03 16:24:52 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fengpin -c fengpin
Info: Found 1 design units, including 1 entities, in source file fengpin.bdf
    Info: Found entity 1: fengpin
Info: Elaborating entity "fengpin" for the top level hierarchy
Warning: Port "ENT" of type 74160 and instance "inst" is missing source signal
Warning: Port "A" of type 74160 and instance "inst" is missing source signal
Warning: Port "B" of type 74160 and instance "inst" is missing source signal
Warning: Port "C" of type 74160 and instance "inst" is missing source signal
Warning: Port "D" of type 74160 and instance "inst" is missing source signal
Warning: Port "LDN" of type 74160 and instance "inst" is missing source signal
Warning: Port "ENP" of type 74160 and instance "inst" is missing source signal
Warning: Port "CLRN" of type 74160 and instance "inst" is missing source signal
Warning: Port "ENT" of type 74160 and instance "inst1" is missing source signal
Warning: Port "A" of type 74160 and instance "inst1" is missing source signal
Warning: Port "B" of type 74160 and instance "inst1" is missing source signal
Warning: Port "C" of type 74160 and instance "inst1" is missing source signal
Warning: Port "D" of type 74160 and instance "inst1" is missing source signal
Warning: Port "LDN" of type 74160 and instance "inst1" is missing source signal
Warning: Port "ENP" of type 74160 and instance "inst1" is missing source signal
Warning: Port "CLRN" of type 74160 and instance "inst1" is missing source signal
Warning: Port "ENT" of type 74160 and instance "inst2" is missing source signal
Warning: Port "A" of type 74160 and instance "inst2" is missing source signal
Warning: Port "B" of type 74160 and instance "inst2" is missing source signal
Warning: Port "C" of type 74160 and instance "inst2" is missing source signal
Warning: Port "D" of type 74160 and instance "inst2" is missing source signal
Warning: Port "LDN" of type 74160 and instance "inst2" is missing source signal
Warning: Port "ENP" of type 74160 and instance "inst2" is missing source signal
Warning: Port "CLRN" of type 74160 and instance "inst2" is missing source signal
Warning: Port "ENT" of type 74160 and instance "inst3" is missing source signal
Warning: Port "A" of type 74160 and instance "inst3" is missing source signal
Warning: Port "B" of type 74160 and instance "inst3" is missing source signal
Warning: Port "C" of type 74160 and instance "inst3" is missing source signal
Warning: Port "D" of type 74160 and instance "inst3" is missing source signal
Warning: Port "LDN" of type 74160 and instance "inst3" is missing source signal
Warning: Port "ENP" of type 74160 and instance "inst3" is missing source signal
Warning: Port "CLRN" of type 74160 and instance "inst3" is missing source signal
Warning: Port "ENT" of type 74160 and instance "inst4" is missing source signal
Warning: Port "A" of type 74160 and instance "inst4" is missing source signal
Warning: Port "B" of type 74160 and instance "inst4" is missing source signal
Warning: Port "C" of type 74160 and instance "inst4" is missing source signal
Warning: Port "D" of type 74160 and instance "inst4" is missing source signal
Warning: Port "LDN" of type 74160 and instance "inst4" is missing source signal
Warning: Port "ENP" of type 74160 and instance "inst4" is missing source signal
Warning: Port "CLRN" of type 74160 and instance "inst4" is missing source signal
Info: Found 1 design units, including 1 entities, in source file e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf
    Info: Found entity 1: 74160
Info: Elaborating entity "74160" for hierarchy "74160:inst4"
Info: Elaborated megafunction instantiation "74160:inst4"
Info: Implemented 27 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 25 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 40 warnings
    Info: Processing ended: Thu Jan 03 16:24:52 2008
    Info: Elapsed time: 00:00:01