chw.vhd

来自「8*8的点阵设计例子可以让刚开始做设计的朋友来参考一下」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity chw is
    port(clk: in std_logic;
         q: out std_logic_vector(1 downto 0));
end chw;

architecture chw_arc of chw is
    begin
      process(clk)
         variable cnt: integer;
         variable tmp:std_logic_vector(1 downto 0);
         begin
           if clk'event and clk='1' then
              if cnt<1000 then
                 cnt:=cnt+1;
              else
                 cnt:=0;
                 if tmp="11"then
                    tmp:="00";
                 else
                    tmp:=tmp+1;
                 end if;
              end if;
            end if;
            q<=tmp;
       end process;
end chw_arc;