chw.tan.qmsg

来自「8*8的点阵设计例子可以让刚开始做设计的朋友来参考一下」· QMSG 代码 · 共 8 行 · 第 1/2 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[19\] register cnt\[3\] 158.1 MHz 6.325 ns Internal " "Info: Clock \"clk\" has Internal fmax of 158.1 MHz between source register \"cnt\[19\]\" and destination register \"cnt\[3\]\" (period= 6.325 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.084 ns + Longest register register " "Info: + Longest register to register delay is 6.084 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[19\] 1 REG LC_X21_Y11_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y11_N3; Fanout = 4; REG Node = 'cnt\[19\]'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "" { cnt[19] } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.590 ns) 1.335 ns LessThan0~457 2 COMB LC_X22_Y11_N7 1 " "Info: 2: + IC(0.745 ns) + CELL(0.590 ns) = 1.335 ns; Loc. = LC_X22_Y11_N7; Fanout = 1; COMB Node = 'LessThan0~457'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "1.335 ns" { cnt[19] LessThan0~457 } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.265 ns) + CELL(0.292 ns) 2.892 ns LessThan0~460 3 COMB LC_X21_Y10_N9 1 " "Info: 3: + IC(1.265 ns) + CELL(0.292 ns) = 2.892 ns; Loc. = LC_X21_Y10_N9; Fanout = 1; COMB Node = 'LessThan0~460'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "1.557 ns" { LessThan0~457 LessThan0~460 } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.292 ns) 3.632 ns LessThan0~461 4 COMB LC_X21_Y10_N8 34 " "Info: 4: + IC(0.448 ns) + CELL(0.292 ns) = 3.632 ns; Loc. = LC_X21_Y10_N8; Fanout = 34; COMB Node = 'LessThan0~461'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "0.740 ns" { LessThan0~460 LessThan0~461 } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.340 ns) + CELL(1.112 ns) 6.084 ns cnt\[3\] 5 REG LC_X21_Y13_N7 4 " "Info: 5: + IC(1.340 ns) + CELL(1.112 ns) = 6.084 ns; Loc. = LC_X21_Y13_N7; Fanout = 4; REG Node = 'cnt\[3\]'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "2.452 ns" { LessThan0~461 cnt[3] } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.286 ns ( 37.57 % ) " "Info: Total cell delay = 2.286 ns ( 37.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.798 ns ( 62.43 % ) " "Info: Total interconnect delay = 3.798 ns ( 62.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "6.084 ns" { cnt[19] LessThan0~457 LessThan0~460 LessThan0~461 cnt[3] } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "6.084 ns" { cnt[19] LessThan0~457 LessThan0~460 LessThan0~461 cnt[3] } { 0.000ns 0.745ns 1.265ns 0.448ns 1.340ns } { 0.000ns 0.590ns 0.292ns 0.292ns 1.112ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.020 ns - Smallest " "Info: - Smallest clock skew is 0.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.962 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 34 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 34; CLK Node = 'clk'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns cnt\[3\] 2 REG LC_X21_Y13_N7 4 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X21_Y13_N7; Fanout = 4; REG Node = 'cnt\[3\]'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "1.493 ns" { clk cnt[3] } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk cnt[3] } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 cnt[3] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.942 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 34 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 34; CLK Node = 'clk'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns cnt\[19\] 2 REG LC_X21_Y11_N3 4 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X21_Y11_N3; Fanout = 4; REG Node = 'cnt\[19\]'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "1.473 ns" { clk cnt[19] } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk cnt[19] } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 cnt[19] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk cnt[3] } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 cnt[3] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk cnt[19] } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 cnt[19] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "6.084 ns" { cnt[19] LessThan0~457 LessThan0~460 LessThan0~461 cnt[3] } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "6.084 ns" { cnt[19] LessThan0~457 LessThan0~460 LessThan0~461 cnt[3] } { 0.000ns 0.745ns 1.265ns 0.448ns 1.340ns } { 0.000ns 0.590ns 0.292ns 0.292ns 1.112ns } } } { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk cnt[3] } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 cnt[3] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk cnt[19] } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 cnt[19] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q\[1\] tmp\[1\] 8.493 ns register " "Info: tco from clock \"clk\" to destination pin \"q\[1\]\" through register \"tmp\[1\]\" is 8.493 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.962 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 34 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 34; CLK Node = 'clk'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns tmp\[1\] 2 REG LC_X21_Y13_N0 2 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X21_Y13_N0; Fanout = 2; REG Node = 'tmp\[1\]'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "1.493 ns" { clk tmp[1] } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk tmp[1] } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 tmp[1] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.307 ns + Longest register pin " "Info: + Longest register to pin delay is 5.307 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tmp\[1\] 1 REG LC_X21_Y13_N0 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y13_N0; Fanout = 2; REG Node = 'tmp\[1\]'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "" { tmp[1] } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.183 ns) + CELL(2.124 ns) 5.307 ns q\[1\] 2 PIN PIN_11 0 " "Info: 2: + IC(3.183 ns) + CELL(2.124 ns) = 5.307 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'q\[1\]'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "5.307 ns" { tmp[1] q[1] } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 40.02 % ) " "Info: Total cell delay = 2.124 ns ( 40.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.183 ns ( 59.98 % ) " "Info: Total interconnect delay = 3.183 ns ( 59.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "5.307 ns" { tmp[1] q[1] } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "5.307 ns" { tmp[1] q[1] } { 0.000ns 3.183ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk tmp[1] } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 tmp[1] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "5.307 ns" { tmp[1] q[1] } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "5.307 ns" { tmp[1] q[1] } { 0.000ns 3.183ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 03 16:21:04 2008 " "Info: Processing ended: Thu Jan 03 16:21:04 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}