fengpin.map.qmsg

来自「8*8的点阵设计例子可以让刚开始做设计的朋友来参考一下」· QMSG 代码 · 共 51 行 · 第 1/2 页

{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "LDN 74160 inst2 " "Warning: Port \"LDN\" of type 74160 and instance \"inst2\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 856 976 448 "inst2" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "ENP 74160 inst2 " "Warning: Port \"ENP\" of type 74160 and instance \"inst2\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 856 976 448 "inst2" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "CLRN 74160 inst2 " "Warning: Port \"CLRN\" of type 74160 and instance \"inst2\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 856 976 448 "inst2" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "ENT 74160 inst3 " "Warning: Port \"ENT\" of type 74160 and instance \"inst3\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1032 1152 448 "inst3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "A 74160 inst3 " "Warning: Port \"A\" of type 74160 and instance \"inst3\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1032 1152 448 "inst3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "B 74160 inst3 " "Warning: Port \"B\" of type 74160 and instance \"inst3\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1032 1152 448 "inst3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "C 74160 inst3 " "Warning: Port \"C\" of type 74160 and instance \"inst3\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1032 1152 448 "inst3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D 74160 inst3 " "Warning: Port \"D\" of type 74160 and instance \"inst3\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1032 1152 448 "inst3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "LDN 74160 inst3 " "Warning: Port \"LDN\" of type 74160 and instance \"inst3\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1032 1152 448 "inst3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "ENP 74160 inst3 " "Warning: Port \"ENP\" of type 74160 and instance \"inst3\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1032 1152 448 "inst3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "CLRN 74160 inst3 " "Warning: Port \"CLRN\" of type 74160 and instance \"inst3\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1032 1152 448 "inst3" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "ENT 74160 inst4 " "Warning: Port \"ENT\" of type 74160 and instance \"inst4\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1216 1336 448 "inst4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "A 74160 inst4 " "Warning: Port \"A\" of type 74160 and instance \"inst4\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1216 1336 448 "inst4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "B 74160 inst4 " "Warning: Port \"B\" of type 74160 and instance \"inst4\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1216 1336 448 "inst4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "C 74160 inst4 " "Warning: Port \"C\" of type 74160 and instance \"inst4\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1216 1336 448 "inst4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D 74160 inst4 " "Warning: Port \"D\" of type 74160 and instance \"inst4\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1216 1336 448 "inst4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "LDN 74160 inst4 " "Warning: Port \"LDN\" of type 74160 and instance \"inst4\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1216 1336 448 "inst4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "ENP 74160 inst4 " "Warning: Port \"ENP\" of type 74160 and instance \"inst4\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1216 1336 448 "inst4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "CLRN 74160 inst4 " "Warning: Port \"CLRN\" of type 74160 and instance \"inst4\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1216 1336 448 "inst4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74160 " "Info: Found entity 1: 74160" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74160 74160:inst4 " "Info: Elaborating entity \"74160\" for hierarchy \"74160:inst4\"" {  } { { "fengpin.bdf" "inst4" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1216 1336 448 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "74160:inst4 " "Info: Elaborated megafunction instantiation \"74160:inst4\"" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 1216 1336 448 "inst4" "" } } } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "27 " "Info: Implemented 27 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "25 " "Info: Implemented 25 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 40 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 40 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 03 16:24:52 2008 " "Info: Processing ended: Thu Jan 03 16:24:52 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}