dianzhen.fit.qmsg

来自「8*8的点阵设计例子可以让刚开始做设计的朋友来参考一下」· QMSG 代码 · 共 42 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 03 16:35:45 2008 " "Info: Processing started: Thu Jan 03 16:35:45 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off dianzhen -c dianzhen " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dianzhen -c dianzhen" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "dianzhen EP1C6T144C8 " "Info: Selected device EP1C6T144C8 for design \"dianzhen\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C3T144C8 " "Info: Device EP1C3T144C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." {  } {  } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "40MHz Global clock in PIN 16 " "Info: Automatically promoted signal \"40MHz\" to use Global clock in PIN 16" {  } { { "dianzhen.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/dianzhen.bdf" { { 184 240 408 200 "40MHz" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "fengpin:inst3\|74160:inst4\|49~26 Global clock " "Info: Automatically promoted signal \"fengpin:inst3\|74160:inst4\|49~26\" to use Global clock" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "fengpin:inst3\|74160:inst1\|49~26 Global clock " "Info: Automatically promoted signal \"fengpin:inst3\|74160:inst1\|49~26\" to use Global clock" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "fengpin:inst3\|74160:inst2\|49~26 Global clock " "Info: Automatically promoted signal \"fengpin:inst3\|74160:inst2\|49~26\" to use Global clock" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "fengpin:inst3\|74160:inst3\|49~26 Global clock " "Info: Automatically promoted signal \"fengpin:inst3\|74160:inst3\|49~26\" to use Global clock" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "fengpin:inst3\|74160:inst\|49~26 Global clock " "Info: Automatically promoted signal \"fengpin:inst3\|74160:inst\|49~26\" to use Global clock" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.904 ns register register " "Info: Estimated most critical path is register to register delay of 5.904 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns chw:inst\|cnt\[21\] 1 REG LAB_X13_Y10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y10; Fanout = 4; REG Node = 'chw:inst\|cnt\[21\]'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "" { chw:inst|cnt[21] } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.621 ns) + CELL(0.114 ns) 1.735 ns chw:inst\|LessThan0~457 2 COMB LAB_X15_Y9 1 " "Info: 2: + IC(1.621 ns) + CELL(0.114 ns) = 1.735 ns; Loc. = LAB_X15_Y9; Fanout = 1; COMB Node = 'chw:inst\|LessThan0~457'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "1.735 ns" { chw:inst|cnt[21] chw:inst|LessThan0~457 } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.674 ns) + CELL(0.590 ns) 2.999 ns chw:inst\|LessThan0~460 3 COMB LAB_X13_Y9 1 " "Info: 3: + IC(0.674 ns) + CELL(0.590 ns) = 2.999 ns; Loc. = LAB_X13_Y9; Fanout = 1; COMB Node = 'chw:inst\|LessThan0~460'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "1.264 ns" { chw:inst|LessThan0~457 chw:inst|LessThan0~460 } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 3.652 ns chw:inst\|LessThan0~461 4 COMB LAB_X13_Y9 34 " "Info: 4: + IC(0.539 ns) + CELL(0.114 ns) = 3.652 ns; Loc. = LAB_X13_Y9; Fanout = 34; COMB Node = 'chw:inst\|LessThan0~461'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "0.653 ns" { chw:inst|LessThan0~460 chw:inst|LessThan0~461 } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.140 ns) + CELL(1.112 ns) 5.904 ns chw:inst\|cnt\[3\] 5 REG LAB_X13_Y12 4 " "Info: 5: + IC(1.140 ns) + CELL(1.112 ns) = 5.904 ns; Loc. = LAB_X13_Y12; Fanout = 4; REG Node = 'chw:inst\|cnt\[3\]'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "2.252 ns" { chw:inst|LessThan0~461 chw:inst|cnt[3] } "NODE_NAME" } } { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.930 ns ( 32.69 % ) " "Info: Total cell delay = 1.930 ns ( 32.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.974 ns ( 67.31 % ) " "Info: Total interconnect delay = 3.974 ns ( 67.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "5.904 ns" { chw:inst|cnt[21] chw:inst|LessThan0~457 chw:inst|LessThan0~460 chw:inst|LessThan0~461 chw:inst|cnt[3] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x12_y0 x23_y10 " "Info: The peak interconnect region extends from location x12_y0 to location x23_y10" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 03 16:35:48 2008 " "Info: Processing ended: Thu Jan 03 16:35:48 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/我的制作/FPGA实验箱/程序/8x8点阵/dianzhen.fit.smsg " "Info: Generated suppressed messages file F:/我的制作/FPGA实验箱/程序/8x8点阵/dianzhen.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}