fengpin.tan.qmsg

来自「8*8的点阵设计例子可以让刚开始做设计的朋友来参考一下」· QMSG 代码 · 共 9 行 · 第 1/3 页

{ "Info" "ITDB_FULL_TCO_RESULT" "40MHz 400Hz 74160:inst4\|6 29.398 ns register " "Info: tco from clock \"40MHz\" to destination pin \"400Hz\" through register \"74160:inst4\|6\" is 29.398 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "40MHz source 24.937 ns + Longest register " "Info: + Longest clock path from clock \"40MHz\" to source register is 24.937 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns 40MHz 1 CLK PIN_17 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = '40MHz'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "" { 40MHz } "NODE_NAME" } } { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 416 264 432 432 "40MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns 74160:inst\|9 2 REG LC_X27_Y10_N8 3 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N8; Fanout = 3; REG Node = '74160:inst\|9'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "1.697 ns" { 40MHz 74160:inst|9 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.564 ns) + CELL(0.292 ns) 4.022 ns 74160:inst\|49~26 3 COMB LC_X27_Y10_N2 4 " "Info: 3: + IC(0.564 ns) + CELL(0.292 ns) = 4.022 ns; Loc. = LC_X27_Y10_N2; Fanout = 4; COMB Node = '74160:inst\|49~26'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "0.856 ns" { 74160:inst|9 74160:inst|49~26 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.429 ns) + CELL(0.935 ns) 8.386 ns 74160:inst1\|6 4 REG LC_X7_Y9_N2 5 " "Info: 4: + IC(3.429 ns) + CELL(0.935 ns) = 8.386 ns; Loc. = LC_X7_Y9_N2; Fanout = 5; REG Node = '74160:inst1\|6'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "4.364 ns" { 74160:inst|49~26 74160:inst1|6 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.583 ns) + CELL(0.292 ns) 9.261 ns 74160:inst1\|49~26 5 COMB LC_X7_Y9_N0 4 " "Info: 5: + IC(0.583 ns) + CELL(0.292 ns) = 9.261 ns; Loc. = LC_X7_Y9_N0; Fanout = 4; COMB Node = '74160:inst1\|49~26'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "0.875 ns" { 74160:inst1|6 74160:inst1|49~26 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.966 ns) + CELL(0.935 ns) 14.162 ns 74160:inst2\|6 6 REG LC_X8_Y10_N9 5 " "Info: 6: + IC(3.966 ns) + CELL(0.935 ns) = 14.162 ns; Loc. = LC_X8_Y10_N9; Fanout = 5; REG Node = '74160:inst2\|6'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "4.901 ns" { 74160:inst1|49~26 74160:inst2|6 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.586 ns) + CELL(0.292 ns) 15.040 ns 74160:inst2\|49~26 7 COMB LC_X8_Y10_N2 4 " "Info: 7: + IC(0.586 ns) + CELL(0.292 ns) = 15.040 ns; Loc. = LC_X8_Y10_N2; Fanout = 4; COMB Node = '74160:inst2\|49~26'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "0.878 ns" { 74160:inst2|6 74160:inst2|49~26 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.463 ns) + CELL(0.935 ns) 19.438 ns 74160:inst3\|6 8 REG LC_X9_Y10_N5 5 " "Info: 8: + IC(3.463 ns) + CELL(0.935 ns) = 19.438 ns; Loc. = LC_X9_Y10_N5; Fanout = 5; REG Node = '74160:inst3\|6'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "4.398 ns" { 74160:inst2|49~26 74160:inst3|6 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.561 ns) + CELL(0.442 ns) 20.441 ns 74160:inst3\|49~26 9 COMB LC_X9_Y10_N2 4 " "Info: 9: + IC(0.561 ns) + CELL(0.442 ns) = 20.441 ns; Loc. = LC_X9_Y10_N2; Fanout = 4; COMB Node = '74160:inst3\|49~26'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "1.003 ns" { 74160:inst3|6 74160:inst3|49~26 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.785 ns) + CELL(0.711 ns) 24.937 ns 74160:inst4\|6 10 REG LC_X1_Y2_N3 5 " "Info: 10: + IC(3.785 ns) + CELL(0.711 ns) = 24.937 ns; Loc. = LC_X1_Y2_N3; Fanout = 5; REG Node = '74160:inst4\|6'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "4.496 ns" { 74160:inst3|49~26 74160:inst4|6 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.238 ns ( 29.03 % ) " "Info: Total cell delay = 7.238 ns ( 29.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "17.699 ns ( 70.97 % ) " "Info: Total interconnect delay = 17.699 ns ( 70.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "24.937 ns" { 40MHz 74160:inst|9 74160:inst|49~26 74160:inst1|6 74160:inst1|49~26 74160:inst2|6 74160:inst2|49~26 74160:inst3|6 74160:inst3|49~26 74160:inst4|6 } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "24.937 ns" { 40MHz 40MHz~out0 74160:inst|9 74160:inst|49~26 74160:inst1|6 74160:inst1|49~26 74160:inst2|6 74160:inst2|49~26 74160:inst3|6 74160:inst3|49~26 74160:inst4|6 } { 0.000ns 0.000ns 0.762ns 0.564ns 3.429ns 0.583ns 3.966ns 0.586ns 3.463ns 0.561ns 3.785ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.935ns 0.292ns 0.935ns 0.292ns 0.935ns 0.442ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.237 ns + Longest register pin " "Info: + Longest register to pin delay is 4.237 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74160:inst4\|6 1 REG LC_X1_Y2_N3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y2_N3; Fanout = 5; REG Node = '74160:inst4\|6'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "" { 74160:inst4|6 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.442 ns) 1.021 ns 74160:inst4\|49~26 2 COMB LC_X1_Y2_N6 1 " "Info: 2: + IC(0.579 ns) + CELL(0.442 ns) = 1.021 ns; Loc. = LC_X1_Y2_N6; Fanout = 1; COMB Node = '74160:inst4\|49~26'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "1.021 ns" { 74160:inst4|6 74160:inst4|49~26 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.092 ns) + CELL(2.124 ns) 4.237 ns 400Hz 3 PIN PIN_33 0 " "Info: 3: + IC(1.092 ns) + CELL(2.124 ns) = 4.237 ns; Loc. = PIN_33; Fanout = 0; PIN Node = '400Hz'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "3.216 ns" { 74160:inst4|49~26 400Hz } "NODE_NAME" } } { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 376 1392 1568 392 "400Hz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.566 ns ( 60.56 % ) " "Info: Total cell delay = 2.566 ns ( 60.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.671 ns ( 39.44 % ) " "Info: Total interconnect delay = 1.671 ns ( 39.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "4.237 ns" { 74160:inst4|6 74160:inst4|49~26 400Hz } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "4.237 ns" { 74160:inst4|6 74160:inst4|49~26 400Hz } { 0.000ns 0.579ns 1.092ns } { 0.000ns 0.442ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "24.937 ns" { 40MHz 74160:inst|9 74160:inst|49~26 74160:inst1|6 74160:inst1|49~26 74160:inst2|6 74160:inst2|49~26 74160:inst3|6 74160:inst3|49~26 74160:inst4|6 } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "24.937 ns" { 40MHz 40MHz~out0 74160:inst|9 74160:inst|49~26 74160:inst1|6 74160:inst1|49~26 74160:inst2|6 74160:inst2|49~26 74160:inst3|6 74160:inst3|49~26 74160:inst4|6 } { 0.000ns 0.000ns 0.762ns 0.564ns 3.429ns 0.583ns 3.966ns 0.586ns 3.463ns 0.561ns 3.785ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.935ns 0.292ns 0.935ns 0.292ns 0.935ns 0.442ns 0.711ns } } } { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "4.237 ns" { 74160:inst4|6 74160:inst4|49~26 400Hz } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "4.237 ns" { 74160:inst4|6 74160:inst4|49~26 400Hz } { 0.000ns 0.579ns 1.092ns } { 0.000ns 0.442ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 03 16:25:02 2008 " "Info: Processing ended: Thu Jan 03 16:25:02 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}