fengpin.tan.qmsg

来自「8*8的点阵设计例子可以让刚开始做设计的朋友来参考一下」· QMSG 代码 · 共 9 行 · 第 1/3 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "40MHz " "Info: Assuming node \"40MHz\" is an undefined clock" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 416 264 432 432 "40MHz" "" } } } } { "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" "" { Assignment "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" 1 { { 0 "40MHz" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "12 " "Warning: Found 12 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "74160:inst\|6 " "Info: Detected ripple clock \"74160:inst\|6\" as buffer" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } } { "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" "" { Assignment "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" 1 { { 0 "74160:inst\|6" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "74160:inst\|9 " "Info: Detected ripple clock \"74160:inst\|9\" as buffer" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } } { "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" "" { Assignment "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" 1 { { 0 "74160:inst\|9" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "74160:inst\|49~26 " "Info: Detected gated clock \"74160:inst\|49~26\" as buffer" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } } { "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" "" { Assignment "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" 1 { { 0 "74160:inst\|49~26" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "74160:inst1\|9 " "Info: Detected ripple clock \"74160:inst1\|9\" as buffer" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } } { "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" "" { Assignment "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" 1 { { 0 "74160:inst1\|9" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "74160:inst1\|6 " "Info: Detected ripple clock \"74160:inst1\|6\" as buffer" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } } { "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" "" { Assignment "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" 1 { { 0 "74160:inst1\|6" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "74160:inst1\|49~26 " "Info: Detected gated clock \"74160:inst1\|49~26\" as buffer" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } } { "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" "" { Assignment "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" 1 { { 0 "74160:inst1\|49~26" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "74160:inst2\|9 " "Info: Detected ripple clock \"74160:inst2\|9\" as buffer" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } } { "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" "" { Assignment "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" 1 { { 0 "74160:inst2\|9" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "74160:inst2\|6 " "Info: Detected ripple clock \"74160:inst2\|6\" as buffer" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } } { "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" "" { Assignment "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" 1 { { 0 "74160:inst2\|6" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "74160:inst2\|49~26 " "Info: Detected gated clock \"74160:inst2\|49~26\" as buffer" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } } { "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" "" { Assignment "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" 1 { { 0 "74160:inst2\|49~26" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "74160:inst3\|9 " "Info: Detected ripple clock \"74160:inst3\|9\" as buffer" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } } { "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" "" { Assignment "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" 1 { { 0 "74160:inst3\|9" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "74160:inst3\|6 " "Info: Detected ripple clock \"74160:inst3\|6\" as buffer" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } } { "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" "" { Assignment "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" 1 { { 0 "74160:inst3\|6" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "74160:inst3\|49~26 " "Info: Detected gated clock \"74160:inst3\|49~26\" as buffer" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } } { "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" "" { Assignment "e:/quartus ii v6.0/zhuang/win/Assignment Editor.qase" 1 { { 0 "74160:inst3\|49~26" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "40MHz register register 74160:inst4\|9 74160:inst4\|7 275.03 MHz Internal " "Info: Clock \"40MHz\" Internal fmax is restricted to 275.03 MHz between source register \"74160:inst4\|9\" and destination register \"74160:inst4\|7\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.300 ns + Longest register register " "Info: + Longest register to register delay is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74160:inst4\|9 1 REG LC_X1_Y2_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y2_N9; Fanout = 3; REG Node = '74160:inst4\|9'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "" { 74160:inst4|9 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.562 ns) + CELL(0.738 ns) 1.300 ns 74160:inst4\|7 2 REG LC_X1_Y2_N2 3 " "Info: 2: + IC(0.562 ns) + CELL(0.738 ns) = 1.300 ns; Loc. = LC_X1_Y2_N2; Fanout = 3; REG Node = '74160:inst4\|7'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "1.300 ns" { 74160:inst4|9 74160:inst4|7 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 304 1032 1096 384 "7" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns ( 56.77 % ) " "Info: Total cell delay = 0.738 ns ( 56.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.562 ns ( 43.23 % ) " "Info: Total interconnect delay = 0.562 ns ( 43.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "1.300 ns" { 74160:inst4|9 74160:inst4|7 } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "1.300 ns" { 74160:inst4|9 74160:inst4|7 } { 0.000ns 0.562ns } { 0.000ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.904 ns - Smallest " "Info: - Smallest clock skew is -0.904 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "40MHz destination 24.033 ns + Shortest register " "Info: + Shortest clock path from clock \"40MHz\" to destination register is 24.033 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns 40MHz 1 CLK PIN_17 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = '40MHz'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "" { 40MHz } "NODE_NAME" } } { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 416 264 432 432 "40MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns 74160:inst\|6 2 REG LC_X27_Y10_N5 5 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N5; Fanout = 5; REG Node = '74160:inst\|6'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "1.697 ns" { 40MHz 74160:inst|6 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.608 ns) + CELL(0.114 ns) 3.888 ns 74160:inst\|49~26 3 COMB LC_X27_Y10_N2 4 " "Info: 3: + IC(0.608 ns) + CELL(0.114 ns) = 3.888 ns; Loc. = LC_X27_Y10_N2; Fanout = 4; COMB Node = '74160:inst\|49~26'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "0.722 ns" { 74160:inst|6 74160:inst|49~26 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.429 ns) + CELL(0.935 ns) 8.252 ns 74160:inst1\|9 4 REG LC_X7_Y9_N3 3 " "Info: 4: + IC(3.429 ns) + CELL(0.935 ns) = 8.252 ns; Loc. = LC_X7_Y9_N3; Fanout = 3; REG Node = '74160:inst1\|9'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "4.364 ns" { 74160:inst|49~26 74160:inst1|9 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.545 ns) + CELL(0.114 ns) 8.911 ns 74160:inst1\|49~26 5 COMB LC_X7_Y9_N0 4 " "Info: 5: + IC(0.545 ns) + CELL(0.114 ns) = 8.911 ns; Loc. = LC_X7_Y9_N0; Fanout = 4; COMB Node = '74160:inst1\|49~26'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "0.659 ns" { 74160:inst1|9 74160:inst1|49~26 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.966 ns) + CELL(0.935 ns) 13.812 ns 74160:inst2\|9 6 REG LC_X8_Y10_N6 3 " "Info: 6: + IC(3.966 ns) + CELL(0.935 ns) = 13.812 ns; Loc. = LC_X8_Y10_N6; Fanout = 3; REG Node = '74160:inst2\|9'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "4.901 ns" { 74160:inst1|49~26 74160:inst2|9 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.549 ns) + CELL(0.114 ns) 14.475 ns 74160:inst2\|49~26 7 COMB LC_X8_Y10_N2 4 " "Info: 7: + IC(0.549 ns) + CELL(0.114 ns) = 14.475 ns; Loc. = LC_X8_Y10_N2; Fanout = 4; COMB Node = '74160:inst2\|49~26'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "0.663 ns" { 74160:inst2|9 74160:inst2|49~26 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.463 ns) + CELL(0.935 ns) 18.873 ns 74160:inst3\|9 8 REG LC_X9_Y10_N6 3 " "Info: 8: + IC(3.463 ns) + CELL(0.935 ns) = 18.873 ns; Loc. = LC_X9_Y10_N6; Fanout = 3; REG Node = '74160:inst3\|9'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "4.398 ns" { 74160:inst2|49~26 74160:inst3|9 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.114 ns) 19.537 ns 74160:inst3\|49~26 9 COMB LC_X9_Y10_N2 4 " "Info: 9: + IC(0.550 ns) + CELL(0.114 ns) = 19.537 ns; Loc. = LC_X9_Y10_N2; Fanout = 4; COMB Node = '74160:inst3\|49~26'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "0.664 ns" { 74160:inst3|9 74160:inst3|49~26 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.785 ns) + CELL(0.711 ns) 24.033 ns 74160:inst4\|7 10 REG LC_X1_Y2_N2 3 " "Info: 10: + IC(3.785 ns) + CELL(0.711 ns) = 24.033 ns; Loc. = LC_X1_Y2_N2; Fanout = 3; REG Node = '74160:inst4\|7'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "4.496 ns" { 74160:inst3|49~26 74160:inst4|7 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 304 1032 1096 384 "7" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.376 ns ( 26.53 % ) " "Info: Total cell delay = 6.376 ns ( 26.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "17.657 ns ( 73.47 % ) " "Info: Total interconnect delay = 17.657 ns ( 73.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "24.033 ns" { 40MHz 74160:inst|6 74160:inst|49~26 74160:inst1|9 74160:inst1|49~26 74160:inst2|9 74160:inst2|49~26 74160:inst3|9 74160:inst3|49~26 74160:inst4|7 } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "24.033 ns" { 40MHz 40MHz~out0 74160:inst|6 74160:inst|49~26 74160:inst1|9 74160:inst1|49~26 74160:inst2|9 74160:inst2|49~26 74160:inst3|9 74160:inst3|49~26 74160:inst4|7 } { 0.000ns 0.000ns 0.762ns 0.608ns 3.429ns 0.545ns 3.966ns 0.549ns 3.463ns 0.550ns 3.785ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.935ns 0.114ns 0.935ns 0.114ns 0.935ns 0.114ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "40MHz source 24.937 ns - Longest register " "Info: - Longest clock path from clock \"40MHz\" to source register is 24.937 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns 40MHz 1 CLK PIN_17 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 4; CLK Node = '40MHz'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "" { 40MHz } "NODE_NAME" } } { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 416 264 432 432 "40MHz" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns 74160:inst\|9 2 REG LC_X27_Y10_N8 3 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N8; Fanout = 3; REG Node = '74160:inst\|9'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "1.697 ns" { 40MHz 74160:inst|9 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.564 ns) + CELL(0.292 ns) 4.022 ns 74160:inst\|49~26 3 COMB LC_X27_Y10_N2 4 " "Info: 3: + IC(0.564 ns) + CELL(0.292 ns) = 4.022 ns; Loc. = LC_X27_Y10_N2; Fanout = 4; COMB Node = '74160:inst\|49~26'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "0.856 ns" { 74160:inst|9 74160:inst|49~26 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.429 ns) + CELL(0.935 ns) 8.386 ns 74160:inst1\|6 4 REG LC_X7_Y9_N2 5 " "Info: 4: + IC(3.429 ns) + CELL(0.935 ns) = 8.386 ns; Loc. = LC_X7_Y9_N2; Fanout = 5; REG Node = '74160:inst1\|6'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "4.364 ns" { 74160:inst|49~26 74160:inst1|6 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.583 ns) + CELL(0.292 ns) 9.261 ns 74160:inst1\|49~26 5 COMB LC_X7_Y9_N0 4 " "Info: 5: + IC(0.583 ns) + CELL(0.292 ns) = 9.261 ns; Loc. = LC_X7_Y9_N0; Fanout = 4; COMB Node = '74160:inst1\|49~26'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "0.875 ns" { 74160:inst1|6 74160:inst1|49~26 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.966 ns) + CELL(0.935 ns) 14.162 ns 74160:inst2\|6 6 REG LC_X8_Y10_N9 5 " "Info: 6: + IC(3.966 ns) + CELL(0.935 ns) = 14.162 ns; Loc. = LC_X8_Y10_N9; Fanout = 5; REG Node = '74160:inst2\|6'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "4.901 ns" { 74160:inst1|49~26 74160:inst2|6 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.586 ns) + CELL(0.292 ns) 15.040 ns 74160:inst2\|49~26 7 COMB LC_X8_Y10_N2 4 " "Info: 7: + IC(0.586 ns) + CELL(0.292 ns) = 15.040 ns; Loc. = LC_X8_Y10_N2; Fanout = 4; COMB Node = '74160:inst2\|49~26'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "0.878 ns" { 74160:inst2|6 74160:inst2|49~26 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.463 ns) + CELL(0.935 ns) 19.438 ns 74160:inst3\|6 8 REG LC_X9_Y10_N5 5 " "Info: 8: + IC(3.463 ns) + CELL(0.935 ns) = 19.438 ns; Loc. = LC_X9_Y10_N5; Fanout = 5; REG Node = '74160:inst3\|6'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "4.398 ns" { 74160:inst2|49~26 74160:inst3|6 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 64 1032 1096 144 "6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.561 ns) + CELL(0.442 ns) 20.441 ns 74160:inst3\|49~26 9 COMB LC_X9_Y10_N2 4 " "Info: 9: + IC(0.561 ns) + CELL(0.442 ns) = 20.441 ns; Loc. = LC_X9_Y10_N2; Fanout = 4; COMB Node = '74160:inst3\|49~26'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "1.003 ns" { 74160:inst3|6 74160:inst3|49~26 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 720 680 744 760 "49" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.785 ns) + CELL(0.711 ns) 24.937 ns 74160:inst4\|9 10 REG LC_X1_Y2_N9 3 " "Info: 10: + IC(3.785 ns) + CELL(0.711 ns) = 24.937 ns; Loc. = LC_X1_Y2_N9; Fanout = 3; REG Node = '74160:inst4\|9'" {  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "4.496 ns" { 74160:inst3|49~26 74160:inst4|9 } "NODE_NAME" } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.238 ns ( 29.03 % ) " "Info: Total cell delay = 7.238 ns ( 29.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "17.699 ns ( 70.97 % ) " "Info: Total interconnect delay = 17.699 ns ( 70.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "24.937 ns" { 40MHz 74160:inst|9 74160:inst|49~26 74160:inst1|6 74160:inst1|49~26 74160:inst2|6 74160:inst2|49~26 74160:inst3|6 74160:inst3|49~26 74160:inst4|9 } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "24.937 ns" { 40MHz 40MHz~out0 74160:inst|9 74160:inst|49~26 74160:inst1|6 74160:inst1|49~26 74160:inst2|6 74160:inst2|49~26 74160:inst3|6 74160:inst3|49~26 74160:inst4|9 } { 0.000ns 0.000ns 0.762ns 0.564ns 3.429ns 0.583ns 3.966ns 0.586ns 3.463ns 0.561ns 3.785ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.935ns 0.292ns 0.935ns 0.292ns 0.935ns 0.442ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "24.033 ns" { 40MHz 74160:inst|6 74160:inst|49~26 74160:inst1|9 74160:inst1|49~26 74160:inst2|9 74160:inst2|49~26 74160:inst3|9 74160:inst3|49~26 74160:inst4|7 } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "24.033 ns" { 40MHz 40MHz~out0 74160:inst|6 74160:inst|49~26 74160:inst1|9 74160:inst1|49~26 74160:inst2|9 74160:inst2|49~26 74160:inst3|9 74160:inst3|49~26 74160:inst4|7 } { 0.000ns 0.000ns 0.762ns 0.608ns 3.429ns 0.545ns 3.966ns 0.549ns 3.463ns 0.550ns 3.785ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.935ns 0.114ns 0.935ns 0.114ns 0.935ns 0.114ns 0.711ns } } } { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "24.937 ns" { 40MHz 74160:inst|9 74160:inst|49~26 74160:inst1|6 74160:inst1|49~26 74160:inst2|6 74160:inst2|49~26 74160:inst3|6 74160:inst3|49~26 74160:inst4|9 } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "24.937 ns" { 40MHz 40MHz~out0 74160:inst|9 74160:inst|49~26 74160:inst1|6 74160:inst1|49~26 74160:inst2|6 74160:inst2|49~26 74160:inst3|6 74160:inst3|49~26 74160:inst4|9 } { 0.000ns 0.000ns 0.762ns 0.564ns 3.429ns 0.583ns 3.966ns 0.586ns 3.463ns 0.561ns 3.785ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.935ns 0.292ns 0.935ns 0.292ns 0.935ns 0.442ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 784 1032 1096 864 "9" "" } } } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 304 1032 1096 384 "7" "" } } } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "1.300 ns" { 74160:inst4|9 74160:inst4|7 } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "1.300 ns" { 74160:inst4|9 74160:inst4|7 } { 0.000ns 0.562ns } { 0.000ns 0.738ns } } } { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "24.033 ns" { 40MHz 74160:inst|6 74160:inst|49~26 74160:inst1|9 74160:inst1|49~26 74160:inst2|9 74160:inst2|49~26 74160:inst3|9 74160:inst3|49~26 74160:inst4|7 } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "24.033 ns" { 40MHz 40MHz~out0 74160:inst|6 74160:inst|49~26 74160:inst1|9 74160:inst1|49~26 74160:inst2|9 74160:inst2|49~26 74160:inst3|9 74160:inst3|49~26 74160:inst4|7 } { 0.000ns 0.000ns 0.762ns 0.608ns 3.429ns 0.545ns 3.966ns 0.549ns 3.463ns 0.550ns 3.785ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.935ns 0.114ns 0.935ns 0.114ns 0.935ns 0.114ns 0.711ns } } } { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "24.937 ns" { 40MHz 74160:inst|9 74160:inst|49~26 74160:inst1|6 74160:inst1|49~26 74160:inst2|6 74160:inst2|49~26 74160:inst3|6 74160:inst3|49~26 74160:inst4|9 } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "24.937 ns" { 40MHz 40MHz~out0 74160:inst|9 74160:inst|49~26 74160:inst1|6 74160:inst1|49~26 74160:inst2|6 74160:inst2|49~26 74160:inst3|6 74160:inst3|49~26 74160:inst4|9 } { 0.000ns 0.000ns 0.762ns 0.564ns 3.429ns 0.583ns 3.966ns 0.586ns 3.463ns 0.561ns 3.785ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.935ns 0.292ns 0.935ns 0.292ns 0.935ns 0.442ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii v6.0/zhuang/win/TimingClosureFloorplan.fld" "" "" { 74160:inst4|7 } "NODE_NAME" } } { "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus ii v6.0/zhuang/win/Technology_Viewer.qrui" "" { 74160:inst4|7 } {  } {  } } } { "74160.bdf" "" { Schematic "e:/quartus ii v6.0/zhuang/libraries/others/maxplus2/74160.bdf" { { 304 1032 1096 384 "7" "" } } } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}