dianzhen.map.qmsg

来自「8*8的点阵设计例子可以让刚开始做设计的朋友来参考一下」· QMSG 代码 · 共 59 行 · 第 1/2 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 03 16:35:42 2008 " "Info: Processing started: Thu Jan 03 16:35:42 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dianzhen -c dianzhen " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dianzhen -c dianzhen" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dianzhen.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file dianzhen.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 dianzhen " "Info: Found entity 1: dianzhen" {  } { { "dianzhen.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/dianzhen.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dianzhen " "Info: Elaborating entity \"dianzhen\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "cora.vhd 2 1 " "Warning: Using design file cora.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cora-corn_arc " "Info: Found design unit 1: cora-corn_arc" {  } { { "cora.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/cora.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cora " "Info: Found entity 1: cora" {  } { { "cora.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/cora.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cora cora:inst2 " "Info: Elaborating entity \"cora\" for hierarchy \"cora:inst2\"" {  } { { "dianzhen.bdf" "inst2" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/dianzhen.bdf" { { 160 768 912 256 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "chw.vhd 2 1 " "Warning: Using design file chw.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 chw-chw_arc " "Info: Found design unit 1: chw-chw_arc" {  } { { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 chw " "Info: Found entity 1: chw" {  } { { "chw.vhd" "" { Text "F:/我的制作/FPGA实验箱/程序/8x8点阵/chw.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "chw chw:inst " "Info: Elaborating entity \"chw\" for hierarchy \"chw:inst\"" {  } { { "dianzhen.bdf" "inst" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/dianzhen.bdf" { { 160 616 712 256 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "fengpin.bdf 1 1 " "Warning: Using design file fengpin.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 fengpin " "Info: Found entity 1: fengpin" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fengpin fengpin:inst3 " "Info: Elaborating entity \"fengpin\" for hierarchy \"fengpin:inst3\"" {  } { { "dianzhen.bdf" "inst3" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/dianzhen.bdf" { { 160 448 576 256 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "ENT 74160 inst " "Warning: Port \"ENT\" of type 74160 and instance \"inst\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 488 608 448 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "A 74160 inst " "Warning: Port \"A\" of type 74160 and instance \"inst\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 488 608 448 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "B 74160 inst " "Warning: Port \"B\" of type 74160 and instance \"inst\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 488 608 448 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "C 74160 inst " "Warning: Port \"C\" of type 74160 and instance \"inst\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 488 608 448 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D 74160 inst " "Warning: Port \"D\" of type 74160 and instance \"inst\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 488 608 448 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "LDN 74160 inst " "Warning: Port \"LDN\" of type 74160 and instance \"inst\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 488 608 448 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "ENP 74160 inst " "Warning: Port \"ENP\" of type 74160 and instance \"inst\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 488 608 448 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "CLRN 74160 inst " "Warning: Port \"CLRN\" of type 74160 and instance \"inst\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 488 608 448 "inst" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "ENT 74160 inst1 " "Warning: Port \"ENT\" of type 74160 and instance \"inst1\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 672 792 448 "inst1" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "A 74160 inst1 " "Warning: Port \"A\" of type 74160 and instance \"inst1\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 672 792 448 "inst1" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "B 74160 inst1 " "Warning: Port \"B\" of type 74160 and instance \"inst1\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 672 792 448 "inst1" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "C 74160 inst1 " "Warning: Port \"C\" of type 74160 and instance \"inst1\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 672 792 448 "inst1" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D 74160 inst1 " "Warning: Port \"D\" of type 74160 and instance \"inst1\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 672 792 448 "inst1" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "LDN 74160 inst1 " "Warning: Port \"LDN\" of type 74160 and instance \"inst1\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 672 792 448 "inst1" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "ENP 74160 inst1 " "Warning: Port \"ENP\" of type 74160 and instance \"inst1\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 672 792 448 "inst1" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "CLRN 74160 inst1 " "Warning: Port \"CLRN\" of type 74160 and instance \"inst1\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 672 792 448 "inst1" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "ENT 74160 inst2 " "Warning: Port \"ENT\" of type 74160 and instance \"inst2\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 856 976 448 "inst2" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "A 74160 inst2 " "Warning: Port \"A\" of type 74160 and instance \"inst2\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 856 976 448 "inst2" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "B 74160 inst2 " "Warning: Port \"B\" of type 74160 and instance \"inst2\" is missing source signal" {  } { { "fengpin.bdf" "" { Schematic "F:/我的制作/FPGA实验箱/程序/8x8点阵/fengpin.bdf" { { 264 856 976 448 "inst2" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}