chw.tan.rpt

8*8的点阵设计例子可以让刚开始做设计的朋友来参考一下

; N/A                                     ; 168.21 MHz ( period = 5.945 ns )                    ; cnt[8]  ; cnt[20] ; clk        ; clk      ; None                        ; None                      ; 5.684 ns                ;
; N/A                                     ; 168.21 MHz ( period = 5.945 ns )                    ; cnt[8]  ; cnt[21] ; clk        ; clk      ; None                        ; None                      ; 5.684 ns                ;
; N/A                                     ; 168.21 MHz ( period = 5.945 ns )                    ; cnt[8]  ; cnt[22] ; clk        ; clk      ; None                        ; None                      ; 5.684 ns                ;
; N/A                                     ; 168.21 MHz ( period = 5.945 ns )                    ; cnt[8]  ; cnt[23] ; clk        ; clk      ; None                        ; None                      ; 5.684 ns                ;
; N/A                                     ; 168.21 MHz ( period = 5.945 ns )                    ; cnt[8]  ; cnt[24] ; clk        ; clk      ; None                        ; None                      ; 5.684 ns                ;
; N/A                                     ; 168.21 MHz ( period = 5.945 ns )                    ; cnt[8]  ; cnt[25] ; clk        ; clk      ; None                        ; None                      ; 5.684 ns                ;
; N/A                                     ; 169.18 MHz ( period = 5.911 ns )                    ; cnt[25] ; cnt[3]  ; clk        ; clk      ; None                        ; None                      ; 5.670 ns                ;
; N/A                                     ; 169.18 MHz ( period = 5.911 ns )                    ; cnt[25] ; cnt[2]  ; clk        ; clk      ; None                        ; None                      ; 5.670 ns                ;
; N/A                                     ; 169.18 MHz ( period = 5.911 ns )                    ; cnt[25] ; cnt[0]  ; clk        ; clk      ; None                        ; None                      ; 5.670 ns                ;
; N/A                                     ; 169.18 MHz ( period = 5.911 ns )                    ; cnt[25] ; cnt[1]  ; clk        ; clk      ; None                        ; None                      ; 5.670 ns                ;
; N/A                                     ; 169.18 MHz ( period = 5.911 ns )                    ; cnt[25] ; cnt[4]  ; clk        ; clk      ; None                        ; None                      ; 5.670 ns                ;
; N/A                                     ; 169.18 MHz ( period = 5.911 ns )                    ; cnt[25] ; cnt[5]  ; clk        ; clk      ; None                        ; None                      ; 5.670 ns                ;
; N/A                                     ; 169.92 MHz ( period = 5.885 ns )                    ; cnt[7]  ; cnt[3]  ; clk        ; clk      ; None                        ; None                      ; 5.644 ns                ;
; N/A                                     ; 169.92 MHz ( period = 5.885 ns )                    ; cnt[7]  ; cnt[2]  ; clk        ; clk      ; None                        ; None                      ; 5.644 ns                ;
; N/A                                     ; 169.92 MHz ( period = 5.885 ns )                    ; cnt[7]  ; cnt[0]  ; clk        ; clk      ; None                        ; None                      ; 5.644 ns                ;
; N/A                                     ; 169.92 MHz ( period = 5.885 ns )                    ; cnt[7]  ; cnt[1]  ; clk        ; clk      ; None                        ; None                      ; 5.644 ns                ;
; N/A                                     ; 169.92 MHz ( period = 5.885 ns )                    ; cnt[7]  ; cnt[4]  ; clk        ; clk      ; None                        ; None                      ; 5.644 ns                ;
; N/A                                     ; 169.92 MHz ( period = 5.885 ns )                    ; cnt[7]  ; cnt[5]  ; clk        ; clk      ; None                        ; None                      ; 5.644 ns                ;
; N/A                                     ; 170.65 MHz ( period = 5.860 ns )                    ; cnt[25] ; cnt[9]  ; clk        ; clk      ; None                        ; None                      ; 5.599 ns                ;
; N/A                                     ; 170.65 MHz ( period = 5.860 ns )                    ; cnt[25] ; cnt[10] ; clk        ; clk      ; None                        ; None                      ; 5.599 ns                ;
; N/A                                     ; 170.65 MHz ( period = 5.860 ns )                    ; cnt[25] ; cnt[11] ; clk        ; clk      ; None                        ; None                      ; 5.599 ns                ;
; N/A                                     ; 170.65 MHz ( period = 5.860 ns )                    ; cnt[25] ; cnt[14] ; clk        ; clk      ; None                        ; None                      ; 5.599 ns                ;
; N/A                                     ; 170.65 MHz ( period = 5.860 ns )                    ; cnt[25] ; cnt[13] ; clk        ; clk      ; None                        ; None                      ; 5.599 ns                ;
; N/A                                     ; 170.65 MHz ( period = 5.860 ns )                    ; cnt[25] ; cnt[12] ; clk        ; clk      ; None                        ; None                      ; 5.599 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;         ;         ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------+
; tco                                                            ;
+-------+--------------+------------+--------+------+------------+
; Slack ; Required tco ; Actual tco ; From   ; To   ; From Clock ;
+-------+--------------+------------+--------+------+------------+
; N/A   ; None         ; 8.493 ns   ; tmp[1] ; q[1] ; clk        ;
; N/A   ; None         ; 7.674 ns   ; tmp[0] ; q[0] ; clk        ;
+-------+--------------+------------+--------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Jan 03 16:21:04 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off chw -c chw --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 158.1 MHz between source register "cnt[19]" and destination register "cnt[3]" (period= 6.325 ns)
    Info: + Longest register to register delay is 6.084 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y11_N3; Fanout = 4; REG Node = 'cnt[19]'
        Info: 2: + IC(0.745 ns) + CELL(0.590 ns) = 1.335 ns; Loc. = LC_X22_Y11_N7; Fanout = 1; COMB Node = 'LessThan0~457'
        Info: 3: + IC(1.265 ns) + CELL(0.292 ns) = 2.892 ns; Loc. = LC_X21_Y10_N9; Fanout = 1; COMB Node = 'LessThan0~460'
        Info: 4: + IC(0.448 ns) + CELL(0.292 ns) = 3.632 ns; Loc. = LC_X21_Y10_N8; Fanout = 34; COMB Node = 'LessThan0~461'
        Info: 5: + IC(1.340 ns) + CELL(1.112 ns) = 6.084 ns; Loc. = LC_X21_Y13_N7; Fanout = 4; REG Node = 'cnt[3]'
        Info: Total cell delay = 2.286 ns ( 37.57 % )
        Info: Total interconnect delay = 3.798 ns ( 62.43 % )
    Info: - Smallest clock skew is 0.020 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.962 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 34; CLK Node = 'clk'
            Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X21_Y13_N7; Fanout = 4; REG Node = 'cnt[3]'
            Info: Total cell delay = 2.180 ns ( 73.60 % )
            Info: Total interconnect delay = 0.782 ns ( 26.40 % )
        Info: - Longest clock path from clock "clk" to source register is 2.942 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 34; CLK Node = 'clk'
            Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X21_Y11_N3; Fanout = 4; REG Node = 'cnt[19]'
            Info: Total cell delay = 2.180 ns ( 74.10 % )
            Info: Total interconnect delay = 0.762 ns ( 25.90 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "q[1]" through register "tmp[1]" is 8.493 ns
    Info: + Longest clock path from clock "clk" to source register is 2.962 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 34; CLK Node = 'clk'
        Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X21_Y13_N0; Fanout = 2; REG Node = 'tmp[1]'
        Info: Total cell delay = 2.180 ns ( 73.60 % )
        Info: Total interconnect delay = 0.782 ns ( 26.40 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.307 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y13_N0; Fanout = 2; REG Node = 'tmp[1]'
        Info: 2: + IC(3.183 ns) + CELL(2.124 ns) = 5.307 ns; Loc. = PIN_11; Fanout = 0; PIN Node = 'q[1]'
        Info: Total cell delay = 2.124 ns ( 40.02 % )
        Info: Total interconnect delay = 3.183 ns ( 59.98 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Jan 03 16:21:04 2008
    Info: Elapsed time: 00:00:01