cnta.fit.rpt

8*8的点阵设计例子可以让刚开始做设计的朋友来参考一下

; Mid Wire Use - Fit Attempt 1                                                   ; 0       ;
; Mid Slack - Fit Attempt 1                                                      ; -2365   ;
; Internal Atom Count - Fit Attempt 1                                            ; 5       ;
; LE/ALM Count - Fit Attempt 1                                                   ; 5       ;
; LAB Count - Fit Attempt 1                                                      ; 2       ;
; Outputs per Lab - Fit Attempt 1                                                ; 1.500   ;
; Inputs per LAB - Fit Attempt 1                                                 ; 0.000   ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.500   ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:2     ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:2     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:2     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:2     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:2     ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:2     ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:2     ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:2     ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:2     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:1;1:1 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:1;1:1 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:2     ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:1;1:1 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:2     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:2     ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:2     ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:2     ;
; LEs in Chains - Fit Attempt 1                                                  ; 0       ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0       ;
; LABs with Chains - Fit Attempt 1                                               ; 0       ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0       ;
; Time - Fit Attempt 1                                                           ; 0       ;
+--------------------------------------------------------------------------------+---------+


+---------------------------------------------+
; Advanced Data - Placement                   ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff    ;
; Early Wire Use - Fit Attempt 1      ; 0     ;
; Early Slack - Fit Attempt 1         ; -1487 ;
; Auto Fit Point 3 - Fit Attempt 1    ; ff    ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff    ;
; Mid Wire Use - Fit Attempt 1        ; 0     ;
; Mid Slack - Fit Attempt 1           ; -1487 ;
; Late Wire Use - Fit Attempt 1       ; 0     ;
; Late Slack - Fit Attempt 1          ; -1487 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff    ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.031 ;
+-------------------------------------+-------+


+---------------------------------------------+
; Advanced Data - Routing                     ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Slack - Fit Attempt 1         ; -577  ;
; Mid Slack - Fit Attempt 1           ; -1039 ;
; Late Slack - Fit Attempt 1          ; -861  ;
; Late Slack - Fit Attempt 1          ; -861  ;
; Late Wire Use - Fit Attempt 1       ; 0     ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.047 ;
+-------------------------------------+-------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Jan 03 15:57:25 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off cnta -c cnta
Info: Selected device EP1C6T144C8 for design "cnta"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP1C3T144C8 is compatible
Info: No exact pin location assignment(s) for 4 pins of 4 total pins
    Info: Pin q[0] not assigned to an exact location on the device
    Info: Pin q[1] not assigned to an exact location on the device
    Info: Pin q[2] not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "clk" to use Global clock in PIN 17
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 3 (unused VREF, 3.30 VCCIO, 0 input, 3 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  19 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  24 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 0.977 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y1; Fanout = 6; REG Node = 'tmp[0]'
    Info: 2: + IC(0.668 ns) + CELL(0.309 ns) = 0.977 ns; Loc. = LAB_X4_Y1; Fanout = 4; REG Node = 'tmp[1]'
    Info: Total cell delay = 0.309 ns ( 31.63 % )
    Info: Total interconnect delay = 0.668 ns ( 68.37 % )
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu Jan 03 15:57:27 2008
    Info: Elapsed time: 00:00:03


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in F:/我的制作/FPGA实验箱/程序/8x8点阵/cnta.fit.smsg.