cnta.vhd

8*8的点阵设计例子可以让刚开始做设计的朋友来参考一下

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cnta is
    port(clk:in std_logic;
         q:out std_logic_vector(2 downto 0));
end cnta;

architecture cnt_arc of cnta is
    begin
      process(clk)
         variable tmp:std_logic_vector(2 downto 0);
           begin
             if clk'event and clk='1' then
               if tmp="111"then
                  tmp:="000";
               else
                  tmp:=tmp+1;
               end if;
             end if;
           q<=tmp-1;
      end process;
end cnt_arc;