cache.vhd

用VHDL语言开发的一个16位的具有5级流水线的CPU设计

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:41:45 05/04/2008 
-- Design Name: 
-- Module Name:    cache - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cache is
    Port (
	 CLK : in std_logic;
	 RESET : in std_logic;
    INPUT_MRD: in std_logic;
	 INPUT_MWR: in std_logic;
    INPUT_AB: in std_logic_vector(15 downto 0);
	 INOUT_DB: inout std_logic_vector(15 downto 0);
	 DELAY : inout std_logic;
	 AB : out std_logic_vector(15 downto 0);
	 DB : inout std_logic_vector(15 downto 0);
	 MRD, MWR : out std_logic
    );
end cache;

architecture Behavioral of cache is

component memory is
	port (
	addr: IN std_logic_VECTOR(5 downto 0);
	clk: IN std_logic;
	din: IN std_logic_VECTOR(7 downto 0);
	dout: OUT std_logic_VECTOR(7 downto 0);
	en: IN std_logic;
	sinit: IN std_logic;
	we: IN std_logic);
end component;

component mem1 is
	port (
	addr: IN std_logic_VECTOR(5 downto 0);
	clk: IN std_logic;
	din: IN std_logic_VECTOR(15 downto 0);
	dout: OUT std_logic_VECTOR(15 downto 0);
	en: IN std_logic;
	sinit: IN std_logic;
	we: IN std_logic);
end component;

--"000" no sleep
--"001" sleep time1
--"011" sleep time2
--"101" sleep time3
--"111" sleep time4
signal STATE: std_logic_vector(1 downto 0);
signal COUNT: std_logic_vector(1 downto 0);
signal TAG: std_logic_vector(7 downto 0);
signal INDEX : std_logic_vector(5 downto 0);
signal SUFFIX: std_logic_vector(1 downto 0);
signal CACHE_WR, CACHE_RD: std_logic;

signal EN, WE, EN1, EN2, EN3, EN4, WE1, WE2, WE3, WE4: std_logic;
signal DIN, DOUT : std_logic_vector(7 downto 0);
signal DIN1, DIN2, DIN3, DIN4 : std_logic_vector(15 downto 0);
signal DOUT1, DOUT2, DOUT3, DOUT4 : std_logic_vector(15 downto 0);
signal SINIT, SINIT1, SINIT2, SINIT3, SINIT4: std_logic;
signal EMPTY: std_logic_vector(63 downto 0);
begin

process(INPUT_MRD, INPUT_MWR, INPUT_AB, INOUT_DB, DELAY, STATE, CLK)
begin

	if CLK = '0' and DELAY = '1' then
		TAG <= INPUT_AB(15 downto 8);
		INDEX <= INPUT_AB(7 downto 2);
		SUFFIX <= INPUT_AB(1 downto 0);
		CACHE_WR <= INPUT_MWR;
		CACHE_RD <= INPUT_MRD;
		
		if INPUT_MRD = '0' then
			EN <= '0';
			EN1 <= '0';
			EN2 <= '0';
			EN3 <= '0';
			EN4 <= '0';
			WE <= '1';
			WE1 <= '1';
			WE2 <= '1';
			WE3 <= '1';
			WE4 <= '1';
		elsif INPUT_MWR = '0' then
			EN <= '0';
			EN1 <= '1';
			EN2 <= '1';
			EN3 <= '1';
			EN4 <= '1';
			WE <= '1';
			WE1 <= '1';
			WE2 <= '1';
			WE3 <= '1';
			WE4 <= '1';
		else
			EN <= '1';
			EN1 <= '1';
			EN2 <= '1';
			EN3 <= '1';
			EN4 <= '1';
			WE <= '1';
			WE1 <= '1';
			WE2 <= '1';
			WE3 <= '1';
			WE4 <= '1';
			
		end if;
	elsif CLK = '0' and DELAY = '0' then
		if CACHE_RD = '0' then
			case STATE is
				when "00" => 	EN <= '1';
									EN1 <= '0';
									EN2 <= '1';
									EN3 <= '1';
									EN4 <= '1';
									WE <= '1';
									WE1 <= '0';
									WE2 <= '1';
									WE3 <= '1';
									WE4 <= '1';
									DIN1 <= DB;
									
				when "01" => 	EN <= '1';
									EN1 <= '1';
									EN2 <= '0';
									EN3 <= '1';
									EN4 <= '1';
									WE <= '1';
									WE1 <= '1';
									WE2 <= '0';
									WE3 <= '1';
									WE4 <= '1';
									DIN2 <= DB;
									
				when "10" => 	EN <= '1';
									EN1 <= '1';
									EN2 <= '1';
									EN3 <= '0';
									EN4 <= '1';
									WE <= '1';
									WE1 <= '1';
									WE2 <= '1';
									WE3 <= '0';
									WE4 <= '1';
									DIN3 <= DB;
									
				when "11" => 	EN <= '0';
									EN1 <= '1';
									EN2 <= '1';
									EN3 <= '1';
									EN4 <= '0';
									WE <= '0';
									WE1 <= '1';
									WE2 <= '1';
									WE3 <= '1';
									WE4 <= '0';
									DIN4 <= DB;
									DIN <= TAG;
									
				when others => EN <= '1';
									EN1 <= '1';
									EN2 <= '1';
									EN3 <= '1';
									EN4 <= '1';
									WE <= '1';
									WE1 <= '1';
									WE2 <= '1';
									WE3 <= '1';
									WE4 <= '1';
			end case;
		elsif CACHE_WR = '0' and INDEX = DOUT(7 downto 0) and  EMPTY(conv_integer(INDEX)) = '0' then
			case SUFFIX is
				when "00" => EN <= '1';
								 EN1 <= '0';
								 EN2 <= '1';
								 EN3 <= '1';
								 EN4 <= '1';
								 WE <= '1';
								 WE1 <= '0';
								 WE2 <= '1';
								 WE3 <= '1';
								 WE4 <= '1';
								 DIN1 <= INOUT_DB;
								 
				when "01" => EN <= '1';
								 EN1 <= '1';
								 EN2 <= '0';
								 EN3 <= '1';
								 EN4 <= '1';
								 WE <= '1';
								 WE1 <= '1';
								 WE2 <= '0';
								 WE3 <= '1';
								 WE4 <= '1';
								 DIN2 <= INOUT_DB;
				when "10" => EN <= '1';
								 EN1 <= '1';
								 EN2 <= '1';
								 EN3 <= '0';
								 EN4 <= '1';
								 WE <= '1';
								 WE1 <= '1';
								 WE2 <= '1';
								 WE3 <= '0';
								 WE4 <= '1';
								 DIN3 <= INOUT_DB;
				when "11" => EN <= '1';
								 EN1 <= '1';
								 EN2 <= '1';
								 EN3 <= '1';
								 EN4 <= '0';
								 WE <= '1';
								 WE1 <= '1';
								 WE2 <= '1';
								 WE3 <= '1';
								 WE4 <= '0';
								 DIN4 <= INOUT_DB;
				when others => EN <= '1';
									EN1 <= '1';
									EN2 <= '1';
									EN3 <= '1';
									EN4 <= '1';
									WE <= '1';
									WE1 <= '1';
									WE2 <= '1';
									WE3 <= '1';
									WE4 <= '1';
			end case;
		elsif CACHE_WR = '0' then
			if STATE = "00" then
					EN <= '1';				
					EN2 <= '1';
					EN3 <= '1';
					EN4 <= '1';
					WE <= '1';					
					WE2 <= '1';
					WE3 <= '1';
					WE4 <= '1';
					EN1 <= '0';
				if SUFFIX = "00" then
					WE1 <= '0';
					DIN1 <= INOUT_DB;
				else
					WE1 <= '1';
				end if;
				
			elsif STATE = "01" then
					EN <= '1';				
					EN1 <= '1';
					EN3 <= '1';
					EN4 <= '1';
					WE <= '1';					
					WE1 <= '1';
					WE3 <= '1';
					WE4 <= '1';
					EN2 <= '0';
				if SUFFIX = "01" then
					WE2 <= '0';
					DIN2 <= INOUT_DB;
				else
					WE2 <= '1';
				end if;
			elsif STATE = "10" then
					EN <= '1';				
					EN1 <= '1';
					EN2 <= '1';
					EN4 <= '1';
					WE <= '1';					
					WE1 <= '1';
					WE2 <= '1';
					WE4 <= '1';
					EN3 <= '0';
				if SUFFIX = "10" then
					WE3 <= '0';
					DIN3 <= INOUT_DB;
				else
					WE3 <= '1';
				end if;
			elsif STATE = "11" then
					EN <= '0';				
					EN1 <= '1';
					EN2 <= '1';
					EN3 <= '1';
					WE <= '0';					
					WE1 <= '1';
					WE2 <= '1';
					WE3 <= '1';
					EN4 <= '0';
					DIN <= TAG;
				if SUFFIX = "11" then
					WE4 <= '0';
					DIN4 <= INOUT_DB;
				else
					WE4 <= '1';
				end if;
			else
				EN <= '1';				
				EN1 <= '1';
				EN2 <= '1';
				EN3 <= '1';
				EN4 <= '1';
				WE <= '1';					
				WE1 <= '1';
				WE2 <= '1';
				WE3 <= '1';
				WE4 <= '1';
			end if;
		end if;
	end if;

end process;

process(CLK, RESET, INPUT_MRD, INPUT_MWR, INPUT_AB, INOUT_DB, DELAY)
begin
	
	if RESET = '0' then
		DELAY <= '1';
		STATE <= "00";
		MRD <= '1';
		MWR <= '1';
		SINIT <= '0';
		SINIT1 <= '0';
		SINIT2 <= '0';
		SINIT3 <= '0';
		SINIT4 <= '0';
		EMPTY <= "1111111111111111111111111111111111111111111111111111111111111111";
	elsif rising_edge(CLK) then
		SINIT <= '1';
		SINIT1 <= '1';
		SINIT2 <= '1';
		SINIT3 <= '1';
		SINIT4 <= '1';
	
		if DELAY = '0' and  COUNT = "00" then
			if CACHE_RD = '0' then
				case STATE is
					when "00" => AB <= TAG & INDEX & "01";
									 MRD <= '0';
									 MWR <= '1';
									 STATE <= "01";
									 COUNT <= "11";
					when "01" => AB <= TAG & INDEX & "10";
									 MRD <= '0';
									 MWR <= '1';
									 STATE <= "10";
									 COUNT <= "11";
					when "10" => AB <= TAG & INDEX & "11";
									 MRD <= '0';
									 MWR <= '1';
									 STATE <= "11";
									 COUNT <= "11";
					when "11" => DELAY <= '1';
									 MRD <= '1';
									 MWR <= '1';
									 EMPTY(conv_integer(INDEX)) <= '0';
									 case SUFFIX is
										when "00" => INOUT_DB <= DOUT1;
										when "01" => INOUT_DB <= DOUT2;
										when "10" => INOUT_DB <= DOUT3;
										when "11" => INOUT_DB <= DOUT4;
										when others => INOUT_DB <= "ZZZZZZZZZZZZZZZZ";
									 end case;
					when others => AB <= "ZZZZZZZZZZZZZZZZ";
										MRD <= '1';
										MWR <= '1';
				end case;
			elsif CACHE_WR = '0' and INDEX = DOUT(7 downto 0) and EMPTY(conv_integer(INDEX)) = '0' then
				DELAY <= '1';
				MRD <= '1';
				MWR <= '1';
			elsif CACHE_WR = '0' then
				if STATE = "00" then
				
					STATE <= "01";
					AB <= TAG & INDEX & "01";
					if SUFFIX = "01" then
						MRD <= '1';
						MWR <= '0';
						DB <= INOUT_DB;
					else
						MRD <= '0';
						MWR <= '1';
					end if;
					
				elsif STATE = "01" then
					STATE <= "10";
					
					AB <= TAG & INDEX & "10";
					if SUFFIX = "10" then
						MRD <= '1';
						MWR <= '0';
						DB <= INOUT_DB;
					else
						MRD <= '0';
						MWR <= '1';
					end if;
					
				elsif STATE = "10" then
					STATE <= "11";
					
					AB <= TAG & INDEX & "11";
					if SUFFIX = "11" then
						MRD <= '1';
						MWR <= '0';
						DB <= INOUT_DB;
					else
						MRD <= '0';
						MWR <= '1';
					end if;					
					
				elsif STATE = "11" then
					STATE <= "00";
					DELAY <= '1';
					MRD <= '1';
					MWR <= '1';
				end if;
			end if;
			
		elsif DELAY = '0' then
			COUNT <= COUNT - 1;
		
		else--if rising_edge(CLK) then
		
			if CACHE_RD = '0' then
		
				if INDEX = DOUT(7 downto 0) and  EMPTY(conv_integer(INDEX)) = '0' then
					
					case SUFFIX is
						when "00" => INOUT_DB <= DOUT1;
						when "01" => INOUT_DB <= DOUT2;
						when "10" => INOUT_DB <= DOUT3;
						when "11" => INOUT_DB <= DOUT4;
						when others => INOUT_DB <= "ZZZZZZZZZZZZZZZZ";
					end case;

				else
					DELAY <= '0';
					COUNT <= "11";
					--state and others
					STATE <= "00";
					AB <= TAG & INDEX & "00";
					MRD <= '0';
					MWR <= '1';
					
				end if;
			
			elsif CACHE_WR = '0' then
				if INDEX = DOUT(7 downto 0) and EMPTY(conv_integer(INDEX)) = '0' then
					DELAY <= '0';
					STATE <= "00";
					AB <= INPUT_AB;
					DB <= INOUT_DB;
					MRD <= '1';
					MWR <= '0';
				else
					DELAY <= '0';
					STATE <= "00";
					AB <= TAG & INDEX & "00";
					if SUFFIX = "00" then
						MRD <= '1';
						MWR <= '0';
						DB <= INOUT_DB;
					else
						MRD <= '0';
						MWR <= '1';
					end if;
					
				end if;
--			else
			
			end if;
		end if;
	end if;
end process;

u0 : memory port map(
	addr => INDEX,
	clk => CLK,
	din => DIN,
	dout => DOUT,
	en => EN,
	sinit => SINIT,
	we => WE
);

u1 : mem1 port map(
		addr => INDEX,
		clk => CLK,
		din => DIN1,
		dout => DOUT1,
		en => EN1,
		sinit => SINIT1,
		we => WE1
);

u2 : mem1 port map(
		addr => INDEX,
		clk => CLK,
		din => DIN2,
		dout => DOUT2,
		en => EN2,
		sinit => SINIT2,
		we => WE2
);

u3 : mem1 port map(
		addr => INDEX,
		clk => CLK,
		din => DIN3,
		dout => DOUT3,
		en => EN3,
		sinit => SINIT3,
		we => WE3
);

u4 : mem1 port map(
		addr => INDEX,
		clk => CLK,
		din => DIN4,
		dout => DOUT4,
		en => EN4,
		sinit => SINIT4,
		we => WE4
);

end Behavioral;