top.par

用VHDL语言开发的一个16位的具有5级流水线的CPU设计

Release 9.1i par J.30
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

DILLY::  Wed May 07 00:27:01 2008

par -w -intstyle ise -ol std -t 1 top_map.ncd top.ncd top.pcf 


Constraints file: top.pcf.
Loading device for application Rf_Device from file 'v150.nph' in environment E:\Xilinx91i.
   "top" is an NCD, version 3.1, device xc2s150, package pq208, speed -6

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 2.375 Volts. (default - Range: 2.375 to 2.625 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".

Device speed data version:  "PRODUCTION 1.27 2006-10-19".


Device Utilization Summary:

   Number of GCLKs                           1 out of 4      25%
   Number of External GCLKIOBs               1 out of 4      25%
      Number of LOCed GCLKIOBs               0 out of 1       0%

   Number of External IOBs                  63 out of 140    45%
      Number of LOCed IOBs                   0 out of 63      0%

   Number of SLICEs                          3 out of 1728    1%


Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98978f) REAL time: 2 secs 

Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.23
Phase 4.23 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.8
.
.
.
.
Phase 7.8 (Checksum:98e959) REAL time: 3 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 3 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 3 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 3 secs 

REAL time consumed by placer: 3 secs 
CPU  time consumed by placer: 2 secs 
Writing design to file top.ncd


Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 

Starting Router

Phase 1: 50 unrouted;       REAL time: 4 secs 

Phase 2: 49 unrouted;       REAL time: 4 secs 

Phase 3: 5 unrouted;       REAL time: 4 secs 

Phase 4: 5 unrouted; (349)      REAL time: 4 secs 

Phase 5: 5 unrouted; (0)      REAL time: 4 secs 

Phase 6: 0 unrouted; (0)      REAL time: 4 secs 

Phase 7: 0 unrouted; (0)      REAL time: 4 secs 

Phase 8: 0 unrouted; (0)      REAL time: 4 secs 

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 2 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           CLK_BUFGP |      GCLKBUF1| No   |    1 |  0.000     |  0.507      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.476
   The MAXIMUM PIN DELAY IS:                               2.824
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.281

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
          15          22          13           0           0           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net CLK | SETUP   |         N/A|     2.590ns|     N/A|           0
  _BUFGP                                    | HOLD    |     2.022ns|            |       0|           0
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 3 secs 

Peak Memory Usage:  115 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file top.ncd



PAR done!