top.vhd

用VHDL语言开发的一个16位的具有5级流水线的CPU设计

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:25:55 03/08/2008 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
	port(
    CI: inout std_logic_vector(31 downto 0);
    CO: in std_logic_vector(31 downto 0);
    DB: inout std_logic_vector(15 downto 0);
    AB: inout std_logic_vector(15 downto 0);
    MUX: in std_logic_vector(0 to 2);
    RUN, RESET : in std_logic;
    CLK: in std_logic;
    KRIX, PRIX: in std_logic;
    MRD, MWR, MCLR, IOW, IOR: inout std_logic;
    CTRL1, CTRL2, CTRL3, CTRL4: inout std_logic;
	 MCLK : out std_logic
	);
end top;

architecture Behavioral of top is

component kernel is
	port(
	 CI: inout std_logic_vector(31 downto 0);
    CO: in std_logic_vector(31 downto 0);
    DB: inout std_logic_vector(15 downto 0);
    AB: inout std_logic_vector(15 downto 0);
    MUX: in std_logic_vector(0 to 2);
    RUN, RESET : in std_logic;
    CLK: in std_logic;
    KRIX, PRIX: in std_logic;
    MRD, MWR, MCLR, IOW, IOR: inout std_logic;
    CTRL1, CTRL2, CTRL3, CTRL4: inout std_logic
	);
end component;

component cache is
    Port (
	 CLK : in std_logic;
	 RESET : in std_logic;
    INPUT_MRD: in std_logic;
	 INPUT_MWR: in std_logic;
    INPUT_AB: in std_logic_vector(15 downto 0);
	 INOUT_DB: inout std_logic_vector(15 downto 0);
	 DELAY : inout std_logic;
	 AB : out std_logic_vector(15 downto 0);
	 DB : inout std_logic_vector(15 downto 0);
	 MRD, MWR : out std_logic
    );
end component;

component four is
	Port(
		clk : in std_logic;
		reset : in std_logic;
		DELAY : in std_logic;
		CPU_CLK: out std_logic;
		clk_out : out std_logic
	);
end component;

signal TEMP_AB, TEMP_DB : std_logic_vector(15 downto 0);
signal TEMP_MRD, TEMP_MWR: std_logic;
signal CPU_CLK : std_logic;
signal DELAY : std_logic;
signal CLK1 : std_logic;
--MCLK, CLK, MRD, MWR, IOW, IOR

--unuseful MCLR
begin
	u1:kernel port map(
		CI => CI,
		CO => CO,
		DB => TEMP_DB,
		AB => TEMP_AB,
		MUX => MUX,
		RUN => RUN,
		RESET => RESET,
		CLK => CPU_CLK,
		KRIX => KRIX,
		PRIX => PRIX,
		MRD => TEMP_MRD,
		MWR => TEMP_MWR,
		MCLR => MCLR,
		IOW => IOW,
		IOR => IOR,
		CTRL1 => CTRL1,
		CTRL2 => CTRL2,
		CTRL3 => CTRL3,
		CTRL4 => CTRL4
	);
	
	u2: cache port map(
		 CLK => CLK1,
		 RESET => RESET,
		 INPUT_MRD => TEMP_MRD,
		 INPUT_MWR => TEMP_MWR,
		 INPUT_AB => TEMP_AB,
		 INOUT_DB => TEMP_DB,
		 DELAY => DELAY,
		 AB => AB,
		 DB => DB,
		 MRD => MRD,
		 MWR => MWR	
	);	
	
	u3: four port map(
		clk => clk,
		reset => reset,
		DELAY => DELAY,
		CPU_CLK => CPU_CLK,
		clk_out => CLK1
	);
	
	MCLK <= CLK1;

end Behavioral;