four.vhd

用VHDL语言开发的一个16位的具有5级流水线的CPU设计

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:54:29 05/04/2008 
-- Design Name: 
-- Module Name:    four - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity four is
Port(
	clk : in std_logic;
	reset : in std_logic;
	DELAY : in std_logic;
	CPU_CLK : inout std_logic;
	clk_out : out std_logic
);
end four;

architecture Behavioral of four is

signal temp_clk : std_logic;
begin

clk_out <= temp_clk;

process (clk, reset, DELAY)
	begin
	if reset = '0' then 
		temp_clk <= '0';
		CPU_CLK <= '0';
	elsif falling_edge(clk) then
	
		temp_clk <= not temp_clk;
		
		if DELAY = '0' then
			CPU_CLK <= CPU_CLK;
		else
			CPU_CLK <= temp_clk;
		end if;
		
	end if;
end process;

end Behavioral;