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📄 top_map.mrp

📁 用VHDL语言开发的一个16位的具有5级流水线的CPU设计
💻 MRP
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The signal "u2/u1/dout<4>" is sourceless and has been removed.The signal "u2/u1/dout<3>" is sourceless and has been removed.The signal "u2/u1/dout<2>" is sourceless and has been removed.The signal "u2/u1/dout<1>" is sourceless and has been removed.The signal "u2/u1/dout<0>" is sourceless and has been removed.The signal "u2/u1/N0" is sourceless and has been removed.The signal "u2/u1/N74" is sourceless and has been removed.The signal "u2/u1/N69" is sourceless and has been removed.The signal "u2/u1/N72" is sourceless and has been removed.The signal "u2/u1/N73" is sourceless and has been removed.The signal "u2/u0/dout<7>" is sourceless and has been removed.The signal "u2/u0/dout<6>" is sourceless and has been removed.The signal "u2/u0/dout<5>" is sourceless and has been removed.The signal "u2/u0/dout<4>" is sourceless and has been removed.The signal "u2/u0/dout<3>" is sourceless and has been removed.The signal "u2/u0/dout<2>" is sourceless and has been removed.The signal "u2/u0/dout<1>" is sourceless and has been removed.The signal "u2/u0/dout<0>" is sourceless and has been removed.The signal "u2/u0/N0" is sourceless and has been removed.The signal "u2/u0/N50" is sourceless and has been removed.The signal "u2/u0/N45" is sourceless and has been removed.The signal "u2/u0/N48" is sourceless and has been removed.The signal "u2/u0/N49" is sourceless and has been removed.The trimmed logic reported below is either:   1. part of a cycle   2. part of disabled logic   3. a side-effect of other trimmed logicThe signal "MCLR" is unused and has been removed. Unused block "MCLR_OBUFT" (TRI) removed.The signal "u2/SINIT" is unused and has been removed. Unused block "u2/SINIT" (FF) removed.Unused block "MCLR" (PAD) removed.Unused block "u2/u0/B10" () removed.Unused block "u2/u0/BU3" (BUF) removed.Unused block "u2/u0/BU4" (BUF) removed.Unused block "u2/u0/BU5" (BUF) removed.Unused block "u2/u0/BU6" (BUF) removed.Unused block "u2/u0/GND" (ZERO) removed.Unused block "u2/u0/VCC" (ONE) removed.Unused block "u2/u1/B10" () removed.Unused block "u2/u1/BU3" (BUF) removed.Unused block "u2/u1/BU4" (BUF) removed.Unused block "u2/u1/BU5" (BUF) removed.Unused block "u2/u1/BU6" (BUF) removed.Unused block "u2/u1/GND" (ZERO) removed.Unused block "u2/u1/VCC" (ONE) removed.Unused block "u2/u2/B10" () removed.Unused block "u2/u2/BU3" (BUF) removed.Unused block "u2/u2/BU4" (BUF) removed.Unused block "u2/u2/BU5" (BUF) removed.Unused block "u2/u2/BU6" (BUF) removed.Unused block "u2/u2/GND" (ZERO) removed.Unused block "u2/u2/VCC" (ONE) removed.Unused block "u2/u3/B10" () removed.Unused block "u2/u3/BU3" (BUF) removed.Unused block "u2/u3/BU4" (BUF) removed.Unused block "u2/u3/BU5" (BUF) removed.Unused block "u2/u3/BU6" (BUF) removed.Unused block "u2/u3/GND" (ZERO) removed.Unused block "u2/u3/VCC" (ONE) removed.Unused block "u2/u4/B10" () removed.Unused block "u2/u4/BU3" (BUF) removed.Unused block "u2/u4/BU4" (BUF) removed.Unused block "u2/u4/BU5" (BUF) removed.Unused block "u2/u4/BU6" (BUF) removed.Unused block "u2/u4/GND" (ZERO) removed.Unused block "u2/u4/VCC" (ONE) removed.Optimized Block(s):TYPE 		BLOCKGND 		XST_GNDVCC 		XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| CLK                                | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       || AB<0>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || AB<1>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || AB<2>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || AB<3>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || AB<4>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || AB<5>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || AB<6>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || AB<7>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || AB<8>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || AB<9>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || AB<10>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || AB<11>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || AB<12>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || AB<13>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || AB<14>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || AB<15>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<0>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<1>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<2>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<3>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<4>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<5>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<6>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<7>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<8>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<9>                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<10>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<11>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<12>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<13>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<14>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<15>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<16>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<17>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<18>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<19>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<20>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<21>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<22>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<23>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<24>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<25>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<26>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<27>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<28>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<29>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<30>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CI<31>                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CTRL1                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CTRL2                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CTRL3                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || CTRL4                              | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || IOR                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || IOW                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || KRIX                               | IOB     | INPUT     | LVTTL       |          |      |          |          |       || MCLK                               | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || MRD                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || MUX<0>                             | IOB     | INPUT     | LVTTL       |          |      |          |          |       || MUX<1>                             | IOB     | INPUT     | LVTTL       |          |      |          |          |       || MUX<2>                             | IOB     | INPUT     | LVTTL       |          |      |          |          |       || MWR                                | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       || PRIX                               | IOB     | INPUT     | LVTTL       |          |      |          |          |       || RESET                              | IOB     | INPUT     | LVTTL       |          |      |          |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group and Partition Summary--------------------------------------------Partition Implementation Status-------------------------------  No Partitions were found in this design.-------------------------------Area Group Information----------------------  No area groups were found in this design.----------------------Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------No timing report for this architecture.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration Strings

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