top_map.mrp

用VHDL语言开发的一个16位的具有5级流水线的CPU设计

Release 9.1i Map J.30
Xilinx Mapping Report File for Design 'top'

Design Information
------------------
Command Line   : E:\Xilinx91i\bin\nt\map.exe -ise F:/project/CPU16/CPU16.ise
-intstyle ise -p xc2s150-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o
top_map.ncd top.ngd top.pcf 
Target Device  : xc2s150
Target Package : pq208
Target Speed   : -6
Mapper Version : spartan2 -- $Revision: 1.36 $
Mapped Date    : Wed May 07 00:26:54 2008

Design Summary
--------------
Number of errors:      0
Number of warnings:    3
Logic Utilization:
  Number of Slice Flip Flops:         1 out of  3,456    1%
  Number of 4 input LUTs:             4 out of  3,456    1%
Logic Distribution:
    Number of occupied Slices:                           3 out of  1,728    1%
    Number of Slices containing only related logic:      3 out of      3  100%
    Number of Slices containing unrelated logic:         0 out of      3    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:         4 out of  3,456    1%
   Number of bonded IOBs:            63 out of    140   45%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  32
Additional JTAG gate count for IOBs:  3,072
Peak Memory Usage:  139 MB
Total REAL time to MAP completion:  3 secs 
Total CPU time to MAP completion:   1 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network RUN has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 120
   more times for the following (max. 5 shown):
   DB<15>,
   DB<14>,
   DB<13>,
   DB<12>,
   DB<11>
   To see the details of these warning messages, please use the -detail switch.
WARNING:MapLib:701 - Signal MCLR connected to top level port MCLR has been
   removed.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
  38 block(s) removed
   2 block(s) optimized away
  99 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "u2/u4/dout<15>" is sourceless and has been removed.
The signal "u2/u4/dout<14>" is sourceless and has been removed.
The signal "u2/u4/dout<13>" is sourceless and has been removed.
The signal "u2/u4/dout<12>" is sourceless and has been removed.
The signal "u2/u4/dout<11>" is sourceless and has been removed.
The signal "u2/u4/dout<10>" is sourceless and has been removed.
The signal "u2/u4/dout<9>" is sourceless and has been removed.
The signal "u2/u4/dout<8>" is sourceless and has been removed.
The signal "u2/u4/dout<7>" is sourceless and has been removed.
The signal "u2/u4/dout<6>" is sourceless and has been removed.
The signal "u2/u4/dout<5>" is sourceless and has been removed.
The signal "u2/u4/dout<4>" is sourceless and has been removed.
The signal "u2/u4/dout<3>" is sourceless and has been removed.
The signal "u2/u4/dout<2>" is sourceless and has been removed.
The signal "u2/u4/dout<1>" is sourceless and has been removed.
The signal "u2/u4/dout<0>" is sourceless and has been removed.
The signal "u2/u4/N0" is sourceless and has been removed.
The signal "u2/u4/N74" is sourceless and has been removed.
The signal "u2/u4/N69" is sourceless and has been removed.
The signal "u2/u4/N72" is sourceless and has been removed.
The signal "u2/u4/N73" is sourceless and has been removed.
The signal "u2/u3/dout<15>" is sourceless and has been removed.
The signal "u2/u3/dout<14>" is sourceless and has been removed.
The signal "u2/u3/dout<13>" is sourceless and has been removed.
The signal "u2/u3/dout<12>" is sourceless and has been removed.
The signal "u2/u3/dout<11>" is sourceless and has been removed.
The signal "u2/u3/dout<10>" is sourceless and has been removed.
The signal "u2/u3/dout<9>" is sourceless and has been removed.
The signal "u2/u3/dout<8>" is sourceless and has been removed.
The signal "u2/u3/dout<7>" is sourceless and has been removed.
The signal "u2/u3/dout<6>" is sourceless and has been removed.
The signal "u2/u3/dout<5>" is sourceless and has been removed.
The signal "u2/u3/dout<4>" is sourceless and has been removed.
The signal "u2/u3/dout<3>" is sourceless and has been removed.
The signal "u2/u3/dout<2>" is sourceless and has been removed.
The signal "u2/u3/dout<1>" is sourceless and has been removed.
The signal "u2/u3/dout<0>" is sourceless and has been removed.
The signal "u2/u3/N0" is sourceless and has been removed.
The signal "u2/u3/N74" is sourceless and has been removed.
The signal "u2/u3/N69" is sourceless and has been removed.
The signal "u2/u3/N72" is sourceless and has been removed.
The signal "u2/u3/N73" is sourceless and has been removed.
The signal "u2/u2/dout<15>" is sourceless and has been removed.
The signal "u2/u2/dout<14>" is sourceless and has been removed.
The signal "u2/u2/dout<13>" is sourceless and has been removed.
The signal "u2/u2/dout<12>" is sourceless and has been removed.
The signal "u2/u2/dout<11>" is sourceless and has been removed.
The signal "u2/u2/dout<10>" is sourceless and has been removed.
The signal "u2/u2/dout<9>" is sourceless and has been removed.
The signal "u2/u2/dout<8>" is sourceless and has been removed.
The signal "u2/u2/dout<7>" is sourceless and has been removed.
The signal "u2/u2/dout<6>" is sourceless and has been removed.
The signal "u2/u2/dout<5>" is sourceless and has been removed.
The signal "u2/u2/dout<4>" is sourceless and has been removed.
The signal "u2/u2/dout<3>" is sourceless and has been removed.
The signal "u2/u2/dout<2>" is sourceless and has been removed.
The signal "u2/u2/dout<1>" is sourceless and has been removed.
The signal "u2/u2/dout<0>" is sourceless and has been removed.
The signal "u2/u2/N0" is sourceless and has been removed.
The signal "u2/u2/N74" is sourceless and has been removed.
The signal "u2/u2/N69" is sourceless and has been removed.
The signal "u2/u2/N72" is sourceless and has been removed.
The signal "u2/u2/N73" is sourceless and has been removed.
The signal "u2/u1/dout<15>" is sourceless and has been removed.
The signal "u2/u1/dout<14>" is sourceless and has been removed.
The signal "u2/u1/dout<13>" is sourceless and has been removed.
The signal "u2/u1/dout<12>" is sourceless and has been removed.
The signal "u2/u1/dout<11>" is sourceless and has been removed.
The signal "u2/u1/dout<10>" is sourceless and has been removed.
The signal "u2/u1/dout<9>" is sourceless and has been removed.
The signal "u2/u1/dout<8>" is sourceless and has been removed.
The signal "u2/u1/dout<7>" is sourceless and has been removed.
The signal "u2/u1/dout<6>" is sourceless and has been removed.
The signal "u2/u1/dout<5>" is sourceless and has been removed.