top_map.map

用VHDL语言开发的一个16位的具有5级流水线的CPU设计

Release 9.1i Map J.30
Xilinx Map Application Log File for Design 'top'

Design Information
------------------
Command Line   : E:\Xilinx91i\bin\nt\map.exe -ise F:/project/CPU16/CPU16.ise
-intstyle ise -p xc2s150-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o
top_map.ncd top.ngd top.pcf 
Target Device  : xc2s150
Target Package : pq208
Target Speed   : -6
Mapper Version : spartan2 -- $Revision: 1.36 $
Mapped Date    : Wed May 07 00:26:54 2008

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    3
Logic Utilization:
  Number of Slice Flip Flops:         1 out of  3,456    1%
  Number of 4 input LUTs:             4 out of  3,456    1%
Logic Distribution:
    Number of occupied Slices:                           3 out of  1,728    1%
    Number of Slices containing only related logic:      3 out of      3  100%
    Number of Slices containing unrelated logic:         0 out of      3    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:         4 out of  3,456    1%
   Number of bonded IOBs:            63 out of    140   45%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  32
Additional JTAG gate count for IOBs:  3,072
Peak Memory Usage:  139 MB
Total REAL time to MAP completion:  3 secs 
Total CPU time to MAP completion:   1 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "top_map.mrp" for details.