kernel.vhd

用VHDL语言开发的一个16位的具有5级流水线的CPU设计

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:24:23 03/08/2008 
-- Design Name: 
-- Module Name:    kernel - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity kernel is
    Port (
    CI: inout std_logic_vector(31 downto 0);
    CO: in std_logic_vector(31 downto 0);
    DB: inout std_logic_vector(15 downto 0);
    AB: inout std_logic_vector(15 downto 0);
    MUX: in std_logic_vector(0 to 2);
    RUN, RESET : in std_logic;
	 CLK: in std_logic;
    KRIX, PRIX: in std_logic;
    MRD, MWR, MCLR, IOW, IOR: inout std_logic;
    CTRL1, CTRL2, CTRL3, CTRL4: inout std_logic
    );
end kernel;

architecture Behavioral of kernel is

signal MCLK : std_logic;
--PC
signal PC: std_logic_vector(15 downto 0);

--Register
signal R0, R1, R2, R3, R4, R5, R6, R7: std_logic_vector(15 downto 0);
signal RIN: std_logic_vector(2 downto 0); 
signal WRE: std_logic;
signal ROUT: std_logic_vector(15 downto 0);

signal TEMP_IMM: std_logic_vector(15 downto 0);
signal TEMP_A, TEMP_B: std_logic_vector(15 downto 0);


--ALU
signal FOUT: std_logic_vector(15 downto 0);
signal COND: std_logic;

signal CWR, CRD, CWRX, CRDX: std_logic;

constant MOV: 	std_logic_vector(4 downto 0) := "00000";
constant ADD: 	std_logic_vector(4 downto 0) := "00001";
constant SUB: 	std_logic_vector(4 downto 0) := "00010";
constant LD: 	std_logic_vector(4 downto 0) := "00011";
constant ST: 	std_logic_vector(4 downto 0) := "00100";
constant ADDI:	std_logic_vector(4 downto 0) := "00101";
constant SUBI:	std_logic_vector(4 downto 0) := "00110";
constant MOVI:	std_logic_vector(4 downto 0) := "00111";
constant MOVHI:std_logic_vector(4 downto 0) := "01000";
constant MOVLI:std_logic_vector(4 downto 0) := "01001";
constant BEQZ:	std_logic_vector(4 downto 0) := "01010";
constant JC: 	std_logic_vector(4 downto 0) := "01011";
constant J: 	std_logic_vector(4 downto 0) := "01100";
--signal ADD, SUB, MOV, ADDI, SUBI, LD, ST, BEQZ, J, JC, MOVI, MOVHI, MOVLI:std_logic_vector(4 downto 0);
--define commands
--	MOV 	<= "00000";
--	ADD 	<= "00001";
--	SUB 	<= "00010";
--	LD  	<= "00011";
--	ST  	<= "00100";
--	ADDI <= "00101";
--	SUBI <= "00110";
--	MOVI <= "00111";
--	MOVHI<= "01000";
--	MOVLI<= "01001";
--	BEQZ <= "01010";
--	JC 	<= "01011";
--	J 	<= "01100";


--register
signal IFID_IR, IFID_NPC: std_logic_vector(15 downto 0);
signal  IDEX_A, IDEX_B, IDEX_IMM, IDEX_IR, ADD_OUT: std_logic_vector(15 downto 0);
signal EXMEM_OUT, EXMEM_IR, EXMEM_B: std_logic_vector(15 downto 0);
signal ADD_COND: std_logic;
signal MEMWB_LMD, MEMWB_OUT, MEMWB_IR: std_logic_vector(15 downto 0);

--T
signal T: std_logic_vector(4 downto 0);

--MUX
signal MUX_R, MUX_A, MUX_B: std_logic_vector(15 downto 0);


--CONTROL
signal CONTROL_A_EXMEM, CONTROL_A_MEMWB, CONTROL_B_EXMEM, CONTROL_B_MEMWB: std_logic;
signal CONTROL_A_COND_EX, CONTROL_A_COND_MEM, CONTROL_A_COND_WB: std_logic;
signal CONTROL_COND_WRITE_IDEX, CONTROL_COND_WRITE_EXMEM, CONTROL_COND_WRITE_MEMWB: std_logic_vector(2 downto 0);
signal CONTROL_MEMORY: std_logic;
signal CONTROL_RWRITE_EXMEM, CONTROL_RWRITE_MEMWB: std_logic_vector(2 downto 0);
signal CONTROL_RREADA_EX, CONTROL_RREADB_EX, CONTROL_RREAD_MEM: std_logic_vector(2 downto 0);
signal CONTROL_TEMP_A, CONTROL_TEMP_B: std_logic;
signal CONTROL_BUBBLE_LD: std_logic;
signal CONTROL_ST_B_EXMEM, CONTROL_ST_B_MEMWB: std_logic;
signal CONTROL_BUBBLE_LD_COND, CONTROL_LD_COND: std_logic;


begin

	CWR <= CWRX or not MCLK;
	CRD <= CRDX or not MCLK;

	MRD <= CRD or AB(15);
	MWR <= CWR or AB(15) or not CLK;
	IOW <= not AB(15) or not AB(1) or CWR or not CLK;
	IOR <= not AB(15) or not AB(0) or CRD;

	CRDX <= '0' when T(0) = '1' or (T(3) = '1' and EXMEM_IR(15 downto 11) = LD) else '1';
	CWRX <= '0' when T(3) = '1' and EXMEM_IR(15 downto 11) = ST else '1';

	AB <= PC when (T(0)='1' and not (EXMEM_IR(15 downto 11) = ST) and not(EXMEM_IR(15 downto 11) = LD)) else
			EXMEM_OUT when (T(3) = '1') else
			"ZZZZZZZZZZZZZZZZ";

-----------------------------------------------T------------------------------------------------------


--T
	process (MCLK,RESET)
	begin	
		if (RESET = '0') then 
			T <= "11111"; 
		elsif (MCLK'event and MCLK = '0') then
			if(CONTROL_BUBBLE_LD = '0') then
				T <= "11000";
			elsif(CONTROL_BUBBLE_LD_COND = '0') then
				T <= "11100";
			elsif(T(0) = '1' and CRDX = '0' and (DB(15 downto 11) = JC or DB(15 downto 11) = J or DB(15 downto 11) = BEQZ)) then
				T <= "11110";
			elsif(IDEX_IR(15 downto 11) = LD or IDEX_IR(15 downto 11) = ST) then
				T <= "11110";
			else
				T <= "11111";
			end if;
		end if;
	end process;


--PC
	process(MCLK, RESET, T(0))
	begin
	if (RESET = '0') then PC <= "0000000000000000";
	elsif (MCLK'event and MCLK = '0') then
		if(ADD_COND = '0') then PC <= ADD_OUT;
		else if (T(0) = '1') then 
			PC <= PC + 1;
			end if;
		end if;
	end if;
	end process;

---------------------------------------T(0)---------------------------------------

--IFID_NPC
	process(MCLK, T(0))
	begin
	if (MCLK'event and MCLK = '0') then
		if (T(0) = '1') then 
			IFID_NPC <= PC + 1;
		end if;
	end if;
	end process;

--IFID_IR
	process(RESET, MCLK, T(0))
	begin
	if (RESET = '0') then IFID_IR <= "1111111111111111";
		else if (MCLK'event and MCLK = '0') then
			if (T(0) = '1') then IFID_IR <= DB;
			elsif(T = "11110") then IFID_IR <= "1111111111111111";
			end if;
		end if;
	end if;
	end process;


-------------------------------------T(1)-------------------------------------------

--TEMP_A
	TEMP_A <= MUX_R when CONTROL_TEMP_A = '0' else
			R0 when IFID_IR(10 downto 8) = "000" else
			R1 when IFID_IR(10 downto 8) = "001" else
			R2 when IFID_IR(10 downto 8) = "010" else
			R3 when IFID_IR(10 downto 8) = "011" else
			R4 when IFID_IR(10 downto 8) = "100" else
			R5 when IFID_IR(10 downto 8) = "101" else
			R6 when IFID_IR(10 downto 8) = "110" else
			R7;

--TEMP_B
	TEMP_B <= MUX_R when CONTROL_TEMP_B = '0' else
			R0 when IFID_IR(4 downto 2) = "000" else
			R1 when IFID_IR(4 downto 2) = "001" else
			R2 when IFID_IR(4 downto 2) = "010" else
			R3 when IFID_IR(4 downto 2) = "011" else
			R4 when IFID_IR(4 downto 2) = "100" else
			R5 when IFID_IR(4 downto 2) = "101" else
			R6 when IFID_IR(4 downto 2) = "110" else
			R7;



--A
	process(MCLK, IFID_IR, T(1))
	begin
	if (MCLK'event and MCLK = '0') then
		if(T(1) = '1') then
			if(CONTROL_TEMP_A = '0') then IDEX_A <= TEMP_A;
			else
			case IFID_IR(10 downto 8) is
				when "000" => IDEX_A <= R0;
				when "001" => IDEX_A <= R1;
				when "010" => IDEX_A <= R2;
				when "011" => IDEX_A <= R3;
				when "100" => IDEX_A <= R4;
				when "101" => IDEX_A <= R5;
				when "110" => IDEX_A <= R6;
				when others => IDEX_A <= R7;
			end case;
			end if;
		end if;	 
	end if;
	end process;

--B
	process(MCLK, IFID_IR, T(1))
	begin
	if (MCLK'event and MCLK = '0') then
		if(T(1) = '1') then
			if(CONTROL_TEMP_B = '0') then IDEX_B <= TEMP_B;
			elsif(IFID_IR(15 downto 11) = ST) then 
			case IFID_IR(7 downto 5) is
				when "000" => IDEX_B <= R0;
				when "001" => IDEX_B <= R1;
				when "010" => IDEX_B <= R2;
				when "011" => IDEX_B <= R3;
				when "100" => IDEX_B <= R4;
				when "101" => IDEX_B <= R5;
				when "110" => IDEX_B <= R6;
				when others => IDEX_B <= R7;
			end case;
			else
			case IFID_IR(4 downto 2) is
				when "000" => IDEX_B <= R0;
				when "001" => IDEX_B <= R1;
				when "010" => IDEX_B <= R2;
				when "011" => IDEX_B <= R3;
				when "100" => IDEX_B <= R4;
				when "101" => IDEX_B <= R5;
				when "110" => IDEX_B <= R6;
				when others => IDEX_B <= R7;
			end case;	
			end if;
		end if;	 
	end if;
	end process;

--TEMP_IMM
	TEMP_IMM <= IFID_IR(7) &	IFID_IR(7) & IFID_IR(7) & IFID_IR(7) & IFID_IR(7) & IFID_IR(7) & IFID_IR(7) & IFID_IR(7) & IFID_IR(7 downto 0) when IFID_IR(15 downto 11) = JC or IFID_IR(15 downto 11) = BEQZ else
		 IFID_IR(10) & IFID_IR(10) & IFID_IR(10) & IFID_IR(10) & IFID_IR(10) & IFID_IR(10 downto 0) when IFID_IR(15 downto 11) = J
		else "0000000000000000";

--IDEX_IMM
	process(MCLK, IFID_IR, T(1))
	begin
	if(MCLK'event and MCLK = '0'and T(1) = '1') then
		if(IFID_IR(15 downto 11) = ST or IFID_IR(15 downto 11) = LD) then
			IDEX_IMM <= IFID_IR(4) & IFID_IR(4) & IFID_IR(4) & IFID_IR(4) & IFID_IR(4) & IFID_IR(4) & IFID_IR(4) & IFID_IR(4) & IFID_IR(4) & IFID_IR(4) & IFID_IR(4) & IFID_IR(4 downto 0);
		elsif(IFID_IR(15 downto 11) = ADDI or IFID_IR(15 downto 11) = SUBI or IFID_IR(15 downto 11) = MOVI or IFID_IR(15 downto 11) = MOVHI or IFID_IR(15 downto 11) = MOVLI or IFID_IR(15 downto 11) = BEQZ or IFID_IR(15 downto 11) = JC) then
			IDEX_IMM <= IFID_IR(7) &IFID_IR(7) &IFID_IR(7) &IFID_IR(7) &IFID_IR(7) &IFID_IR(7) &IFID_IR(7) &IFID_IR(7) &IFID_IR(7 downto 0);	
		elsif(IFID_IR(15 downto 11) = J) then
			IDEX_IMM <= IFID_IR(10) & IFID_IR(10) & IFID_IR(10) & IFID_IR(10) & IFID_IR(10) & IFID_IR(10 downto 0);
		end if;
	end if;
	end process;

--IDEX_IR
	process(MCLK, RESET, T(1))
	begin
	if(RESET = '0') then IDEX_IR <= "1111111111111111";
	else if(MCLK'event and MCLK = '0') then
		if(T(1) = '1') then IDEX_IR <= IFID_IR;
		elsif(T = "11100") then IDEX_IR <= "1111111111111111";
	end if;
	end if;
	end if;
	end process;


--ADD_OUT
	ADD_OUT <= IFID_NPC + TEMP_IMM;


		
--ADD_COND
	ADD_COND <= COND;

	ROUT <= TEMP_A;


	COND <= '0' when  (IFID_IR(15 downto 11) = BEQZ and FOUT = "0000000000000000" and CONTROL_A_COND_EX = '0')
				or (IFID_IR(15 downto 11) = BEQZ and KRIX = '0' and AB = "1000000000000100" and CONTROL_A_COND_EX = '1' and CONTROL_LD_COND = '0' and not (T = "11100"))
				or (IFID_IR(15 downto 11) = BEQZ and PRIX = '0' and AB = "1000000000001000" and CONTROL_A_COND_EX = '1' and CONTROL_LD_COND = '0' and not (T = "11100"))
				or (IFID_IR(15 downto 11) = BEQZ and DB = "0000000000000000" and not(AB = "1000000000000100" or AB = "1000000000001000")	and CONTROL_A_COND_EX = '1' and CONTROL_LD_COND = '0' and not (T = "11100"))
				or (IFID_IR(15 downto 11) = BEQZ and DB = "0000000000000000" and CONTROL_A_COND_EX = '1' and CONTROL_A_COND_MEM = '0' and CONTROL_LD_COND = '1' and EXMEM_IR(15 downto 11) = LD)
				or (IFID_IR(15 downto 11) = BEQZ and EXMEM_OUT = "0000000000000000" and CONTROL_A_COND_EX = '1' and CONTROL_A_COND_MEM = '0' and CONTROL_LD_COND = '1' and not (EXMEM_IR(15 downto 11) = LD))
				or (IFID_IR(15 downto 11) = BEQZ and MUX_R = "0000000000000000" and CONTROL_A_COND_EX = '1' and CONTROL_A_COND_MEM = '1' and CONTROL_LD_COND = '1' and CONTROL_A_COND_WB = '0') 
				or (IFID_IR(15 downto 11) = BEQZ and ROUT = "0000000000000000" and CONTROL_A_COND_EX = '1' and CONTROL_A_COND_MEM = '1' and CONTROL_LD_COND = '1' and CONTROL_A_COND_WB = '1')
				or (IFID_IR(15 downto 11) = JC and FOUT(15) = '1' and CONTROL_A_COND_EX = '0')
				or (IFID_IR(15 downto 11) = JC and DB(15) = '1' and CONTROL_A_COND_EX = '1' and CONTROL_LD_COND = '0' and not (T = "11100"))
				or (IFID_IR(15 downto 11) = JC and DB(15) = '1' and CONTROL_A_COND_EX = '1' and CONTROL_LD_COND = '1' and CONTROL_A_COND_MEM = '0' and EXMEM_IR(15 downto 11) = LD)
				or (IFID_IR(15 downto 11) = JC and EXMEM_OUT(15) = '1' and CONTROL_A_COND_EX = '1' and CONTROL_LD_COND = '1' and CONTROL_A_COND_MEM = '0' and not (EXMEM_IR(15 downto 11) = LD))
				or (IFID_IR(15 downto 11) = JC and MUX_R(15) = '1' and CONTROL_A_COND_EX = '1' and CONTROL_LD_COND = '1' and CONTROL_A_COND_MEM = '1' and CONTROL_A_COND_WB = '0') 
				or (IFID_IR(15 downto 11) = JC and ROUT(15) = '1' and CONTROL_A_COND_EX = '1' and CONTROL_LD_COND = '1' and CONTROL_A_COND_MEM = '1' and CONTROL_A_COND_WB = '1') 
				or IFID_IR(15 downto 11) = J 
		else '1';


---------------------------------------T(2)------------------------------------------

--ALU

	MUX_A <= 	EXMEM_OUT when CONTROL_A_EXMEM = '0' else
			MEMWB_LMD when CONTROL_A_EXMEM = '1' and CONTROL_A_MEMWB = '0' and MEMWB_IR(15 downto 11) = LD	else
			MEMWB_OUT when CONTROL_A_EXMEM = '1' and CONTROL_A_MEMWB = '0' and not (MEMWB_IR(15 downto 11) = LD)
				else IDEX_A;
	MUX_B <= 	EXMEM_OUT when CONTROL_B_EXMEM = '0' else
			MEMWB_LMD when CONTROL_B_EXMEM = '1' and CONTROL_B_MEMWB = '0' and MEMWB_IR(15 downto 11) = LD else
			MEMWB_OUT when CONTROL_B_EXMEM = '1' and CONTROL_B_MEMWB = '0' and not (MEMWB_IR(15 downto 11) = LD) else
			IDEX_IMM when (IDEX_IR(15 downto 11) = MOVI 
					or IDEX_IR(15 downto 11) = ADDI 
					or IDEX_IR(15 downto 11) = SUBI 
					or IDEX_IR(15 downto 11) = MOVI 
					or IDEX_IR(15 downto 11) = MOVHI 
					or IDEX_IR(15 downto 11) = MOVLI
					or IDEX_IR(15 downto 11) = ST
					or IDEX_IR(15 downto 11) = LD) 
				else IDEX_B;
 

	FOUT <= MUX_A when IDEX_IR(15 downto 11) = MOV else
		   MUX_B(7) & MUX_B(7) & MUX_B(7) & MUX_B(7) & MUX_B(7) & MUX_B(7) & MUX_B(7) & MUX_B(7) & MUX_B(7 downto 0) when IDEX_IR(15 downto 11) = MOVI else
		   MUX_B(7 downto 0) & MUX_A(7 downto 0) when IDEX_IR(15 downto 11) = MOVHI else
		   MUX_A(15 downto 8) & MUX_B(7 downto 0) when IDEX_IR(15 downto 11) = MOVLI else
		   MUX_A + MUX_B when IDEX_IR(15 downto 11) = ADD or IDEX_IR(15 downto 11) = ADDI or IDEX_IR(15 downto 11) = LD or IDEX_IR(15 downto 11) = ST else
		   MUX_A - MUX_B when IDEX_IR(15 downto 11) = SUB or IDEX_IR(15 downto 11) = SUBI else
		   "0000000000000000";

--EXMEM_IR
	process(MCLK, RESET, T(2))
	begin
	if(RESET = '0') then EXMEM_IR <= "1111111111111111";
	else if(MCLK'event and MCLK = '0') then
		if(T(2) = '1') then EXMEM_IR <= IDEX_IR;
		else EXMEM_IR <= "1111111111111111";
	end if;
	end if;
	end if;
	end process;

--EXMEM_OUT
	process(MCLK, RESET, T(2), FOUT)
	begin
	if(RESET = '0') then EXMEM_OUT <= "0000000000000000";
	else if(MCLK'event and MCLK = '0') then
		if(T(2) = '1') then EXMEM_OUT <= FOUT;
		end if;
	end if;
	end if;
	end process;

--EXMEM_B
	process(MCLK, RESET, T(2), IDEX_B)
	begin
	if(MCLK'event and MCLK = '0') then
		if(T(2) = '1' and IDEX_IR(15 downto 11) = ST) then
			if(CONTROL_ST_B_EXMEM = '0') then EXMEM_B <= EXMEM_OUT;
			elsif(CONTROL_ST_B_MEMWB = '0' and CONTROL_ST_B_EXMEM = '1') then EXMEM_B <= MUX_R;
			else
				EXMEM_B <= IDEX_B;
			end if;
		end if;
	end if;
	end process;

---------------------------------------T(3)----------------------------------------

--MEMWB_IR
	process(MCLK, RESET, T(3))
	begin
	if(RESET = '0') then MEMWB_IR <= "1111111111111111";
	else if(MCLK'event and MCLK = '0') then
		if(T(3) = '1') then MEMWB_IR <= EXMEM_IR;
		end if;
	end if;
	end if;
	end process;

--MEMWB_OUT
	process(T(3), RESET, MCLK)
	begin
	if(RESET = '0') then MEMWB_OUT <= "0000000000000000";
	else if(MCLK'event and MCLK = '0') then
		if(T(3) = '1') then MEMWB_OUT <= EXMEM_OUT;
		end if;
	end if;
	end if;
	end process;

----MEMWB_LMD----
	process(T(3), MCLK, RESET)
	begin