top.syr

用VHDL语言开发的一个16位的具有5级流水线的CPU设计

WARNING:Xst - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst - Property "use_dsp48" is not applicable for this technology.
WARNING:Xst - Property "use_dsp48" is not applicable for this technology.
    Found 16-bit tristate buffer for signal <AB>.
    Found 16-bit tristate buffer for signal <DB>.
    Found 32-bit 8-to-1 multiplexer for signal <CI>.
    Found 1-bit tristate buffer for signal <MCLR>.
    Found 16-bit adder for signal <ADD_OUT>.
    Found 3-bit comparator equal for signal <CONTROL_A_COND_EX$cmp_eq0000> created at line 727.
    Found 3-bit comparator equal for signal <CONTROL_A_COND_MEM$cmp_eq0000> created at line 745.
    Found 3-bit comparator equal for signal <CONTROL_A_COND_WB$cmp_eq0000> created at line 763.
    Found 3-bit comparator equal for signal <CONTROL_A_EXMEM$cmp_eq0000> created at line 550.
    Found 3-bit comparator equal for signal <CONTROL_A_MEMWB$cmp_eq0000> created at line 575.
    Found 3-bit comparator equal for signal <CONTROL_B_EXMEM$cmp_eq0000> created at line 601.
    Found 3-bit comparator equal for signal <CONTROL_B_MEMWB$cmp_eq0000> created at line 619.
    Found 3-bit comparator equal for signal <CONTROL_BUBBLE_LD$cmp_eq0000> created at line 782.
    Found 3-bit comparator equal for signal <CONTROL_BUBBLE_LD$cmp_eq0010> created at line 782.
    Found 3-bit comparator equal for signal <CONTROL_BUBBLE_LD_COND$cmp_eq0001> created at line 841.
    Found 3-bit tristate buffer for signal <CONTROL_COND_WRITE_EXMEM>.
    Found 3-bit tristate buffer for signal <CONTROL_COND_WRITE_IDEX>.
    Found 3-bit tristate buffer for signal <CONTROL_COND_WRITE_MEMWB>.
    Found 3-bit comparator equal for signal <CONTROL_LD_COND$cmp_eq0000> created at line 845.
    Found 3-bit comparator equal for signal <CONTROL_MEMORY$cmp_eq0000> created at line 688.
    Found 3-bit tristate buffer for signal <CONTROL_RWRITE_EXMEM>.
    Found 3-bit tristate buffer for signal <CONTROL_RWRITE_MEMWB>.
    Found 3-bit comparator equal for signal <CONTROL_ST_B_EXMEM$cmp_eq0000> created at line 806.
    Found 3-bit comparator equal for signal <CONTROL_ST_B_MEMWB$cmp_eq0000> created at line 822.
    Found 3-bit comparator equal for signal <CONTROL_TEMP_A$cmp_eq0000> created at line 640.
    Found 3-bit comparator equal for signal <CONTROL_TEMP_B$cmp_eq0000> created at line 666.
    Found 16-bit register for signal <EXMEM_B>.
    Found 16-bit register for signal <EXMEM_IR>.
    Found 16-bit register for signal <EXMEM_OUT>.
    Found 16-bit addsub for signal <FOUT$addsub0000>.
    Found 16-bit register for signal <IDEX_A>.
    Found 16-bit register for signal <IDEX_B>.
    Found 16-bit register for signal <IDEX_IMM>.
    Found 16-bit register for signal <IDEX_IR>.
    Found 16-bit register for signal <IFID_IR>.
    Found 16-bit register for signal <IFID_NPC>.
    Found 16-bit adder for signal <IFID_NPC$add0000> created at line 185.
    Found 16-bit register for signal <MEMWB_IR>.
    Found 16-bit register for signal <MEMWB_LMD>.
    Found 16-bit register for signal <MEMWB_OUT>.
    Found 16-bit tristate buffer for signal <MUX_R>.
    Found 16-bit up counter for signal <PC>.
    Found 16-bit register for signal <R0>.
    Found 16-bit register for signal <R1>.
    Found 16-bit register for signal <R2>.
    Found 16-bit register for signal <R3>.
    Found 16-bit register for signal <R4>.
    Found 16-bit register for signal <R5>.
    Found 16-bit register for signal <R6>.
    Found 16-bit register for signal <R7>.
    Found 16-bit 8-to-1 multiplexer for signal <R7$mux0000>.
    Found 3-bit tristate buffer for signal <RIN>.
    Found 5-bit register for signal <T>.
    Summary:
	inferred   1 Counter(s).
	inferred 325 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred  16 Comparator(s).
	inferred  48 Multiplexer(s).
	inferred  67 Tristate(s).
Unit <kernel> synthesized.


Synthesizing Unit <four>.
    Related source file is "F:/project/CPU16/four.vhd".
    Found 1-bit register for signal <CPU_CLK>.
    Found 1-bit register for signal <temp_clk>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <four> synthesized.


Synthesizing Unit <cache>.
    Related source file is "F:/project/CPU16/cache.vhd".
    Register <SINIT1> equivalent to <SINIT> has been removed
    Register <SINIT2> equivalent to <SINIT> has been removed
    Register <SINIT3> equivalent to <SINIT> has been removed
    Register <SINIT4> equivalent to <SINIT> has been removed
    Found finite state machine <FSM_0> for signal <STATE>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 13                                             |
    | Inputs             | 3                                              |
    | Outputs            | 12                                             |
    | Clock              | CLK (rising_edge)                              |
    | Clock enable       | STATE$not0000 (positive)                       |
    | Reset              | RESET (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:737 - Found 1-bit latch for signal <CACHE_WR>.
WARNING:Xst:737 - Found 8-bit latch for signal <DIN>.
WARNING:Xst:737 - Found 1-bit latch for signal <EN>.
WARNING:Xst:737 - Found 1-bit latch for signal <EN1>.
WARNING:Xst:737 - Found 1-bit latch for signal <EN2>.
WARNING:Xst:737 - Found 1-bit latch for signal <EN3>.
WARNING:Xst:737 - Found 1-bit latch for signal <EN4>.
WARNING:Xst:737 - Found 1-bit latch for signal <WE1>.
WARNING:Xst:737 - Found 1-bit latch for signal <WE2>.
WARNING:Xst:737 - Found 1-bit latch for signal <WE3>.
WARNING:Xst:737 - Found 1-bit latch for signal <WE4>.
WARNING:Xst:737 - Found 1-bit latch for signal <WE>.
WARNING:Xst:737 - Found 16-bit latch for signal <DIN1>.
WARNING:Xst:737 - Found 16-bit latch for signal <DIN2>.
WARNING:Xst:737 - Found 16-bit latch for signal <DIN3>.
WARNING:Xst:737 - Found 16-bit latch for signal <DIN4>.
WARNING:Xst:737 - Found 1-bit latch for signal <CACHE_RD>.
WARNING:Xst:737 - Found 2-bit latch for signal <SUFFIX>.
WARNING:Xst:737 - Found 8-bit latch for signal <TAG>.
WARNING:Xst:737 - Found 6-bit latch for signal <INDEX>.
WARNING:Xst - Property "use_dsp48" is not applicable for this technology.
    Found 16-bit register for signal <AB>.
    Found 16-bit register for signal <DB>.
    Found 1-bit register for signal <MRD>.
    Found 1-bit register for signal <MWR>.
    Found 16-bit register for signal <INOUT_DB>.
    Found 1-bit register for signal <DELAY>.
    Found 1-bit 64-to-1 multiplexer for signal <$varindex0000> created at line 386.
    Found 2-bit register for signal <COUNT>.
    Found 2-bit subtractor for signal <COUNT$addsub0000> created at line 446.
    Found 8-bit comparator equal for signal <COUNT$cmp_eq0000> created at line 452.
    Found 8-bit comparator not equal for signal <DB$cmp_ne0001> created at line 474.
    Found 64-bit register for signal <EMPTY>.
    Found 1-bit register for signal <SINIT>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred 118 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   2 Comparator(s).
	inferred   1 Multiplexer(s).
Unit <cache> synthesized.


Synthesizing Unit <top>.
    Related source file is "F:/project/CPU16/top.vhd".
Unit <top> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 4
 16-bit adder                                          : 2
 16-bit addsub                                         : 1
 2-bit subtractor                                      : 1
# Counters                                             : 1
 16-bit up counter                                     : 1
# Registers                                            : 95
 1-bit register                                        : 70
 16-bit register                                       : 23
 2-bit register                                        : 1
 5-bit register                                        : 1
# Latches                                              : 20
 1-bit latch                                           : 12
 16-bit latch                                          : 4
 2-bit latch                                           : 1
 6-bit latch                                           : 1
 8-bit latch                                           : 2
# Comparators                                          : 18
 3-bit comparator equal                                : 16