prev_cmp_vga.qmsg

VGA显示的例子（VHDL语言）

{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 12 19:41:03 2008 " "Info: Processing started: Thu Jun 12 19:41:03 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off VGA -c VGA " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off VGA -c VGA" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "143 " "Info: Allocated 143 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 12 19:41:14 2008 " "Info: Processing ended: Thu Jun 12 19:41:14 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 12 19:41:17 2008 " "Info: Processing started: Thu Jun 12 19:41:17 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off VGA -c VGA --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off VGA -c VGA --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 128 -48 120 144 "clk" "" } } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "reset " "Info: Assuming node \"reset\" is an undefined clock" {  } { { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 144 -48 120 160 "reset" "" } } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "VGAsingl:inst\|FS\[5\] " "Info: Detected ripple clock \"VGAsingl:inst\|FS\[5\]\" as buffer" {  } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 10 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGAsingl:inst\|FS\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "VGAsingl:inst\|CC\[4\] " "Info: Detected ripple clock \"VGAsingl:inst\|CC\[4\]\" as buffer" {  } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGAsingl:inst\|CC\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register VGAsingl:inst\|CC\[0\] register VGAsingl:inst\|CC\[4\] 233.05 MHz 4.291 ns Internal " "Info: Clock \"clk\" has Internal fmax of 233.05 MHz between source register \"VGAsingl:inst\|CC\[0\]\" and destination register \"VGAsingl:inst\|CC\[4\]\" (period= 4.291 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.857 ns + Longest register register " "Info: + Longest register to register delay is 2.857 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsingl:inst\|CC\[0\] 1 REG LCFF_X33_Y10_N13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y10_N13; Fanout = 4; REG Node = 'VGAsingl:inst\|CC\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGAsingl:inst|CC[0] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.517 ns) + CELL(0.621 ns) 1.138 ns VGAsingl:inst\|Add2~61 2 COMB LCCOMB_X33_Y10_N12 2 " "Info: 2: + IC(0.517 ns) + CELL(0.621 ns) = 1.138 ns; Loc. = LCCOMB_X33_Y10_N12; Fanout = 2; COMB Node = 'VGAsingl:inst\|Add2~61'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.138 ns" { VGAsingl:inst|CC[0] VGAsingl:inst|Add2~61 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 1.328 ns VGAsingl:inst\|Add2~63 3 COMB LCCOMB_X33_Y10_N14 2 " "Info: 3: + IC(0.000 ns) + CELL(0.190 ns) = 1.328 ns; Loc. = LCCOMB_X33_Y10_N14; Fanout = 2; COMB Node = 'VGAsingl:inst\|Add2~63'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { VGAsingl:inst|Add2~61 VGAsingl:inst|Add2~63 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.414 ns VGAsingl:inst\|Add2~65 4 COMB LCCOMB_X33_Y10_N16 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.414 ns; Loc. = LCCOMB_X33_Y10_N16; Fanout = 2; COMB Node = 'VGAsingl:inst\|Add2~65'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { VGAsingl:inst|Add2~63 VGAsingl:inst|Add2~65 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.500 ns VGAsingl:inst\|Add2~67 5 COMB LCCOMB_X33_Y10_N18 1 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.500 ns; Loc. = LCCOMB_X33_Y10_N18; Fanout = 1; COMB Node = 'VGAsingl:inst\|Add2~67'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { VGAsingl:inst|Add2~65 VGAsingl:inst|Add2~67 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 2.006 ns VGAsingl:inst\|Add2~68 6 COMB LCCOMB_X33_Y10_N20 1 " "Info: 6: + IC(0.000 ns) + CELL(0.506 ns) = 2.006 ns; Loc. = LCCOMB_X33_Y10_N20; Fanout = 1; COMB Node = 'VGAsingl:inst\|Add2~68'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { VGAsingl:inst|Add2~67 VGAsingl:inst|Add2~68 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.370 ns) 2.749 ns VGAsingl:inst\|CC~201 7 COMB LCCOMB_X33_Y10_N6 1 " "Info: 7: + IC(0.373 ns) + CELL(0.370 ns) = 2.749 ns; Loc. = LCCOMB_X33_Y10_N6; Fanout = 1; COMB Node = 'VGAsingl:inst\|CC~201'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.743 ns" { VGAsingl:inst|Add2~68 VGAsingl:inst|CC~201 } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.857 ns VGAsingl:inst\|CC\[4\] 8 REG LCFF_X33_Y10_N7 7 " "Info: 8: + IC(0.000 ns) + CELL(0.108 ns) = 2.857 ns; Loc. = LCFF_X33_Y10_N7; Fanout = 7; REG Node = 'VGAsingl:inst\|CC\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { VGAsingl:inst|CC~201 VGAsingl:inst|CC[4] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.967 ns ( 68.85 % ) " "Info: Total cell delay = 1.967 ns ( 68.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.890 ns ( 31.15 % ) " "Info: Total interconnect delay = 0.890 ns ( 31.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.857 ns" { VGAsingl:inst|CC[0] VGAsingl:inst|Add2~61 VGAsingl:inst|Add2~63 VGAsingl:inst|Add2~65 VGAsingl:inst|Add2~67 VGAsingl:inst|Add2~68 VGAsingl:inst|CC~201 VGAsingl:inst|CC[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.857 ns" { VGAsingl:inst|CC[0] {} VGAsingl:inst|Add2~61 {} VGAsingl:inst|Add2~63 {} VGAsingl:inst|Add2~65 {} VGAsingl:inst|Add2~67 {} VGAsingl:inst|Add2~68 {} VGAsingl:inst|CC~201 {} VGAsingl:inst|CC[4] {} } { 0.000ns 0.517ns 0.000ns 0.000ns 0.000ns 0.000ns 0.373ns 0.000ns } { 0.000ns 0.621ns 0.190ns 0.086ns 0.086ns 0.506ns 0.370ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-1.170 ns - Smallest " "Info: - Smallest clock skew is -1.170 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.245 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.448 ns) + CELL(0.970 ns) 3.558 ns VGAsingl:inst\|FS\[5\] 2 REG LCFF_X12_Y10_N7 4 " "Info: 2: + IC(1.448 ns) + CELL(0.970 ns) = 3.558 ns; Loc. = LCFF_X12_Y10_N7; Fanout = 4; REG Node = 'VGAsingl:inst\|FS\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.418 ns" { clk VGAsingl:inst|FS[5] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.021 ns) + CELL(0.666 ns) 6.245 ns VGAsingl:inst\|CC\[4\] 3 REG LCFF_X33_Y10_N7 7 " "Info: 3: + IC(2.021 ns) + CELL(0.666 ns) = 6.245 ns; Loc. = LCFF_X33_Y10_N7; Fanout = 7; REG Node = 'VGAsingl:inst\|CC\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.687 ns" { VGAsingl:inst|FS[5] VGAsingl:inst|CC[4] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 44.45 % ) " "Info: Total cell delay = 2.776 ns ( 44.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.469 ns ( 55.55 % ) " "Info: Total interconnect delay = 3.469 ns ( 55.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.245 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|CC[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.245 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|CC[4] {} } { 0.000ns 0.000ns 1.448ns 2.021ns } { 0.000ns 1.140ns 0.970ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.415 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.415 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.448 ns) + CELL(0.970 ns) 3.558 ns VGAsingl:inst\|FS\[5\] 2 REG LCFF_X12_Y10_N7 4 " "Info: 2: + IC(1.448 ns) + CELL(0.970 ns) = 3.558 ns; Loc. = LCFF_X12_Y10_N7; Fanout = 4; REG Node = 'VGAsingl:inst\|FS\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.418 ns" { clk VGAsingl:inst|FS[5] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.311 ns) + CELL(0.000 ns) 5.869 ns VGAsingl:inst\|FS\[5\]~clkctrl 3 COMB CLKCTRL_G0 4 " "Info: 3: + IC(2.311 ns) + CELL(0.000 ns) = 5.869 ns; Loc. = CLKCTRL_G0; Fanout = 4; COMB Node = 'VGAsingl:inst\|FS\[5\]~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.311 ns" { VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.880 ns) + CELL(0.666 ns) 7.415 ns VGAsingl:inst\|CC\[0\] 4 REG LCFF_X33_Y10_N13 4 " "Info: 4: + IC(0.880 ns) + CELL(0.666 ns) = 7.415 ns; Loc. = LCFF_X33_Y10_N13; Fanout = 4; REG Node = 'VGAsingl:inst\|CC\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.546 ns" { VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[0] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 37.44 % ) " "Info: Total cell delay = 2.776 ns ( 37.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.639 ns ( 62.56 % ) " "Info: Total interconnect delay = 4.639 ns ( 62.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.415 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.415 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|FS[5]~clkctrl {} VGAsingl:inst|CC[0] {} } { 0.000ns 0.000ns 1.448ns 2.311ns 0.8