vga.tan.qmsg

VGA显示的例子（VHDL语言）

{ "Info" "ITDB_FULL_TCO_RESULT" "clk b VGAsingl:inst\|LL\[3\] 19.653 ns register " "Info: tco from clock \"clk\" to destination pin \"b\" through register \"VGAsingl:inst\|LL\[3\]\" is 19.653 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.041 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.041 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.308 ns) + CELL(0.970 ns) 3.418 ns VGAsingl:inst\|FS\[5\] 2 REG LCFF_X7_Y9_N15 4 " "Info: 2: + IC(1.308 ns) + CELL(0.970 ns) = 3.418 ns; Loc. = LCFF_X7_Y9_N15; Fanout = 4; REG Node = 'VGAsingl:inst\|FS\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.278 ns" { clk VGAsingl:inst|FS[5] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.615 ns) + CELL(0.970 ns) 5.003 ns VGAsingl:inst\|CC\[4\] 3 REG LCFF_X8_Y9_N7 7 " "Info: 3: + IC(0.615 ns) + CELL(0.970 ns) = 5.003 ns; Loc. = LCFF_X8_Y9_N7; Fanout = 7; REG Node = 'VGAsingl:inst\|CC\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.585 ns" { VGAsingl:inst|FS[5] VGAsingl:inst|CC[4] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.516 ns) + CELL(0.000 ns) 6.519 ns VGAsingl:inst\|CC\[4\]~clkctrl 4 COMB CLKCTRL_G0 9 " "Info: 4: + IC(1.516 ns) + CELL(0.000 ns) = 6.519 ns; Loc. = CLKCTRL_G0; Fanout = 9; COMB Node = 'VGAsingl:inst\|CC\[4\]~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.516 ns" { VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.856 ns) + CELL(0.666 ns) 8.041 ns VGAsingl:inst\|LL\[3\] 5 REG LCFF_X18_Y10_N11 8 " "Info: 5: + IC(0.856 ns) + CELL(0.666 ns) = 8.041 ns; Loc. = LCFF_X18_Y10_N11; Fanout = 8; REG Node = 'VGAsingl:inst\|LL\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.522 ns" { VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[3] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 46.59 % ) " "Info: Total cell delay = 3.746 ns ( 46.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.295 ns ( 53.41 % ) " "Info: Total interconnect delay = 4.295 ns ( 53.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.041 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.041 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|CC[4] {} VGAsingl:inst|CC[4]~clkctrl {} VGAsingl:inst|LL[3] {} } { 0.000ns 0.000ns 1.308ns 0.615ns 1.516ns 0.856ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 53 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.308 ns + Longest register pin " "Info: + Longest register to pin delay is 11.308 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsingl:inst\|LL\[3\] 1 REG LCFF_X18_Y10_N11 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y10_N11; Fanout = 8; REG Node = 'VGAsingl:inst\|LL\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGAsingl:inst|LL[3] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.482 ns) + CELL(0.651 ns) 2.133 ns VGAsingl:inst\|B~1372 2 COMB LCCOMB_X18_Y7_N0 1 " "Info: 2: + IC(1.482 ns) + CELL(0.651 ns) = 2.133 ns; Loc. = LCCOMB_X18_Y7_N0; Fanout = 1; COMB Node = 'VGAsingl:inst\|B~1372'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.133 ns" { VGAsingl:inst|LL[3] VGAsingl:inst|B~1372 } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.094 ns) + CELL(0.370 ns) 3.597 ns VGAsingl:inst\|B~1374 3 COMB LCCOMB_X21_Y7_N10 1 " "Info: 3: + IC(1.094 ns) + CELL(0.370 ns) = 3.597 ns; Loc. = LCCOMB_X21_Y7_N10; Fanout = 1; COMB Node = 'VGAsingl:inst\|B~1374'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.464 ns" { VGAsingl:inst|B~1372 VGAsingl:inst|B~1374 } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.393 ns) + CELL(0.650 ns) 4.640 ns VGAsingl:inst\|B~1378 4 COMB LCCOMB_X21_Y7_N22 1 " "Info: 4: + IC(0.393 ns) + CELL(0.650 ns) = 4.640 ns; Loc. = LCCOMB_X21_Y7_N22; Fanout = 1; COMB Node = 'VGAsingl:inst\|B~1378'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.043 ns" { VGAsingl:inst|B~1374 VGAsingl:inst|B~1378 } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.623 ns) 5.625 ns VGAsingl:inst\|B~1382 5 COMB LCCOMB_X21_Y7_N2 1 " "Info: 5: + IC(0.362 ns) + CELL(0.623 ns) = 5.625 ns; Loc. = LCCOMB_X21_Y7_N2; Fanout = 1; COMB Node = 'VGAsingl:inst\|B~1382'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.985 ns" { VGAsingl:inst|B~1378 VGAsingl:inst|B~1382 } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.577 ns) + CELL(3.106 ns) 11.308 ns b 6 PIN PIN_114 0 " "Info: 6: + IC(2.577 ns) + CELL(3.106 ns) = 11.308 ns; Loc. = PIN_114; Fanout = 0; PIN Node = 'b'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.683 ns" { VGAsingl:inst|B~1382 b } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 192 472 648 208 "b" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.400 ns ( 47.75 % ) " "Info: Total cell delay = 5.400 ns ( 47.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.908 ns ( 52.25 % ) " "Info: Total interconnect delay = 5.908 ns ( 52.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.308 ns" { VGAsingl:inst|LL[3] VGAsingl:inst|B~1372 VGAsingl:inst|B~1374 VGAsingl:inst|B~1378 VGAsingl:inst|B~1382 b } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.308 ns" { VGAsingl:inst|LL[3] {} VGAsingl:inst|B~1372 {} VGAsingl:inst|B~1374 {} VGAsingl:inst|B~1378 {} VGAsingl:inst|B~1382 {} b {} } { 0.000ns 1.482ns 1.094ns 0.393ns 0.362ns 2.577ns } { 0.000ns 0.651ns 0.370ns 0.650ns 0.623ns 3.106ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.041 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.041 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|CC[4] {} VGAsingl:inst|CC[4]~clkctrl {} VGAsingl:inst|LL[3] {} } { 0.000ns 0.000ns 1.308ns 0.615ns 1.516ns 0.856ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.308 ns" { VGAsingl:inst|LL[3] VGAsingl:inst|B~1372 VGAsingl:inst|B~1374 VGAsingl:inst|B~1378 VGAsingl:inst|B~1382 b } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.308 ns" { VGAsingl:inst|LL[3] {} VGAsingl:inst|B~1372 {} VGAsingl:inst|B~1374 {} VGAsingl:inst|B~1378 {} VGAsingl:inst|B~1382 {} b {} } { 0.000ns 1.482ns 1.094ns 0.393ns 0.362ns 2.577ns } { 0.000ns 0.651ns 0.370ns 0.650ns 0.623ns 3.106ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "reset r 15.428 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"r\" is 15.428 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns reset 1 CLK PIN_56 5 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_56; Fanout = 5; CLK Node = 'reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 144 -48 120 160 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.928 ns) + CELL(0.370 ns) 8.282 ns VGAsingl:inst\|R~546 2 COMB LCCOMB_X21_Y7_N4 1 " "Info: 2: + IC(6.928 ns) + CELL(0.370 ns) = 8.282 ns; Loc. = LCCOMB_X21_Y7_N4; Fanout = 1; COMB Node = 'VGAsingl:inst\|R~546'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.298 ns" { reset VGAsingl:inst|R~546 } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.027 ns) + CELL(0.616 ns) 9.925 ns VGAsingl:inst\|R~547 3 COMB LCCOMB_X21_Y7_N20 1 " "Info: 3: + IC(1.027 ns) + CELL(0.616 ns) = 9.925 ns; Loc. = LCCOMB_X21_Y7_N20; Fanout = 1; COMB Node = 'VGAsingl:inst\|R~547'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.643 ns" { VGAsingl:inst|R~546 VGAsingl:inst|R~547 } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.417 ns) + CELL(3.086 ns) 15.428 ns r 4 PIN PIN_112 0 " "Info: 4: + IC(2.417 ns) + CELL(3.086 ns) = 15.428 ns; Loc. = PIN_112; Fanout = 0; PIN Node = 'r'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.503 ns" { VGAsingl:inst|R~547 r } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 160 464 640 176 "r" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.056 ns ( 32.77 % ) " "Info: Total cell delay = 5.056 ns ( 32.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.372 ns ( 67.23 % ) " "Info: Total interconnect delay = 10.372 ns ( 67.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.428 ns" { reset VGAsingl:inst|R~546 VGAsingl:inst|R~547 r } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.428 ns" { reset {} reset~combout {} VGAsingl:inst|R~546 {} VGAsingl:inst|R~547 {} r {} } { 0.000ns 0.000ns 6.928ns 1.027ns 2.417ns } { 0.000ns 0.984ns 0.370ns 0.616ns 3.086ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 12 19:48:40 2008 " "Info: Processing ended: Thu Jun 12 19:48:40 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}