vga.tan.qmsg

VGA显示的例子（VHDL语言）

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "reset register register VGAsingl:inst\|MMD\[1\] VGAsingl:inst\|MMD\[0\] 360.1 MHz Internal " "Info: Clock \"reset\" Internal fmax is restricted to 360.1 MHz between source register \"VGAsingl:inst\|MMD\[1\]\" and destination register \"VGAsingl:inst\|MMD\[0\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.777 ns " "Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.776 ns + Longest register register " "Info: + Longest register to register delay is 0.776 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsingl:inst\|MMD\[1\] 1 REG LCFF_X21_Y7_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y7_N1; Fanout = 5; REG Node = 'VGAsingl:inst\|MMD\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGAsingl:inst|MMD[1] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.466 ns) + CELL(0.202 ns) 0.668 ns VGAsingl:inst\|MMD~42 2 COMB LCCOMB_X21_Y7_N6 1 " "Info: 2: + IC(0.466 ns) + CELL(0.202 ns) = 0.668 ns; Loc. = LCCOMB_X21_Y7_N6; Fanout = 1; COMB Node = 'VGAsingl:inst\|MMD~42'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.668 ns" { VGAsingl:inst|MMD[1] VGAsingl:inst|MMD~42 } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.776 ns VGAsingl:inst\|MMD\[0\] 3 REG LCFF_X21_Y7_N7 9 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.776 ns; Loc. = LCFF_X21_Y7_N7; Fanout = 9; REG Node = 'VGAsingl:inst\|MMD\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { VGAsingl:inst|MMD~42 VGAsingl:inst|MMD[0] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.310 ns ( 39.95 % ) " "Info: Total cell delay = 0.310 ns ( 39.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.466 ns ( 60.05 % ) " "Info: Total interconnect delay = 0.466 ns ( 60.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.776 ns" { VGAsingl:inst|MMD[1] VGAsingl:inst|MMD~42 VGAsingl:inst|MMD[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.776 ns" { VGAsingl:inst|MMD[1] {} VGAsingl:inst|MMD~42 {} VGAsingl:inst|MMD[0] {} } { 0.000ns 0.466ns 0.000ns } { 0.000ns 0.202ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "reset destination 4.085 ns + Shortest register " "Info: + Shortest clock path from clock \"reset\" to destination register is 4.085 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns reset 1 CLK PIN_56 5 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_56; Fanout = 5; CLK Node = 'reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 144 -48 120 160 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.435 ns) + CELL(0.666 ns) 4.085 ns VGAsingl:inst\|MMD\[0\] 2 REG LCFF_X21_Y7_N7 9 " "Info: 2: + IC(2.435 ns) + CELL(0.666 ns) = 4.085 ns; Loc. = LCFF_X21_Y7_N7; Fanout = 9; REG Node = 'VGAsingl:inst\|MMD\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.101 ns" { reset VGAsingl:inst|MMD[0] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.650 ns ( 40.39 % ) " "Info: Total cell delay = 1.650 ns ( 40.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.435 ns ( 59.61 % ) " "Info: Total interconnect delay = 2.435 ns ( 59.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.085 ns" { reset VGAsingl:inst|MMD[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.085 ns" { reset {} reset~combout {} VGAsingl:inst|MMD[0] {} } { 0.000ns 0.000ns 2.435ns } { 0.000ns 0.984ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "reset source 4.085 ns - Longest register " "Info: - Longest clock path from clock \"reset\" to source register is 4.085 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns reset 1 CLK PIN_56 5 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_56; Fanout = 5; CLK Node = 'reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 144 -48 120 160 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.435 ns) + CELL(0.666 ns) 4.085 ns VGAsingl:inst\|MMD\[1\] 2 REG LCFF_X21_Y7_N1 5 " "Info: 2: + IC(2.435 ns) + CELL(0.666 ns) = 4.085 ns; Loc. = LCFF_X21_Y7_N1; Fanout = 5; REG Node = 'VGAsingl:inst\|MMD\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.101 ns" { reset VGAsingl:inst|MMD[1] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.650 ns ( 40.39 % ) " "Info: Total cell delay = 1.650 ns ( 40.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.435 ns ( 59.61 % ) " "Info: Total interconnect delay = 2.435 ns ( 59.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.085 ns" { reset VGAsingl:inst|MMD[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.085 ns" { reset {} reset~combout {} VGAsingl:inst|MMD[1] {} } { 0.000ns 0.000ns 2.435ns } { 0.000ns 0.984ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.085 ns" { reset VGAsingl:inst|MMD[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.085 ns" { reset {} reset~combout {} VGAsingl:inst|MMD[0] {} } { 0.000ns 0.000ns 2.435ns } { 0.000ns 0.984ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.085 ns" { reset VGAsingl:inst|MMD[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.085 ns" { reset {} reset~combout {} VGAsingl:inst|MMD[1] {} } { 0.000ns 0.000ns 2.435ns } { 0.000ns 0.984ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.776 ns" { VGAsingl:inst|MMD[1] VGAsingl:inst|MMD~42 VGAsingl:inst|MMD[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.776 ns" { VGAsingl:inst|MMD[1] {} VGAsingl:inst|MMD~42 {} VGAsingl:inst|MMD[0] {} } { 0.000ns 0.466ns 0.000ns } { 0.000ns 0.202ns 0.108ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.085 ns" { reset VGAsingl:inst|MMD[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.085 ns" { reset {} reset~combout {} VGAsingl:inst|MMD[0] {} } { 0.000ns 0.000ns 2.435ns } { 0.000ns 0.984ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.085 ns" { reset VGAsingl:inst|MMD[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.085 ns" { reset {} reset~combout {} VGAsingl:inst|MMD[1] {} } { 0.000ns 0.000ns 2.435ns } { 0.000ns 0.984ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGAsingl:inst|MMD[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { VGAsingl:inst|MMD[0] {} } {  } {  } "" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 23 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 2 " "Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "VGAsingl:inst\|CC\[4\] VGAsingl:inst\|CC\[3\] clk 130 ps " "Info: Found hold time violation between source  pin or register \"VGAsingl:inst\|CC\[4\]\" and destination pin or register \"VGAsingl:inst\|CC\[3\]\" for clock \"clk\" (Hold time is 130 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.930 ns + Largest " "Info: + Largest clock skew is 2.930 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.629 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.629 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.308 ns) + CELL(0.970 ns) 3.418 ns VGAsingl:inst\|FS\[5\] 2 REG LCFF_X7_Y9_N15 4 " "Info: 2: + IC(1.308 ns) + CELL(0.970 ns) = 3.418 ns; Loc. = LCFF_X7_Y9_N15; Fanout = 4; REG Node = 'VGAsingl:inst\|FS\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.278 ns" { clk VGAsingl:inst|FS[5] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.668 ns) + CELL(0.000 ns) 6.086 ns VGAsingl:inst\|FS\[5\]~clkctrl 3 COMB CLKCTRL_G6 4 " "Info: 3: + IC(2.668 ns) + CELL(0.000 ns) = 6.086 ns; Loc. = CLKCTRL_G6; Fanout = 4; COMB Node = 'VGAsingl:inst\|FS\[5\]~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.668 ns" { VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.877 ns) + CELL(0.666 ns) 7.629 ns VGAsingl:inst\|CC\[3\] 4 REG LCFF_X8_Y9_N5 7 " "Info: 4: + IC(0.877 ns) + CELL(0.666 ns) = 7.629 ns; Loc. = LCFF_X8_Y9_N5; Fanout = 7; REG Node = 'VGAsingl:inst\|CC\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.543 ns" { VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[3] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 36.39 % ) " "Info: Total cell delay = 2.776 ns ( 36.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.853 ns ( 63.61 % ) " "Info: Total interconnect delay = 4.853 ns ( 63.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.629 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.629 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|FS[5]~clkctrl {} VGAsingl:inst|CC[3] {} } { 0.000ns 0.000ns 1.308ns 2.668ns 0.877ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 4.699 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 4.699 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.308 ns) + CELL(0.970 ns) 3.418 ns VGAsingl:inst\|FS\[5\] 2 REG LCFF_X7_Y9_N15 4 " "Info: 2: + IC(1.308 ns) + CELL(0.970 ns) = 3.418 ns; Loc. = LCFF_X7_Y9_N15; Fanout = 4; REG Node = 'VGAsingl:inst\|FS\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.278 ns" { clk VGAsingl:inst|FS[5] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.615 ns) + CELL(0.666 ns) 4.699 ns VGAsingl:inst\|CC\[4\] 3 REG LCFF_X8_Y9_N7 7 " "Info: 3: + IC(0.615 ns) + CELL(0.666 ns) = 4.699 ns; Loc. = LCFF_X8_Y9_N7; Fanout = 7; REG Node = 'VGAsingl:inst\|CC\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.281 ns" { VGAsingl:inst|FS[5] VGAsingl:inst|CC[4] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 59.08 % ) " "Info: Total cell delay = 2.776 ns ( 59.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.923 ns ( 40.92 % ) " "Info: Total interconnect delay = 1.923 ns ( 40.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.699 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|CC[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.699 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|CC[4] {} } { 0.000ns 0.000ns 1.308ns 0.615ns } { 0.000ns 1.140ns 0.970ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.629 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.629 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|FS[5]~clkctrl {} VGAsingl:inst|CC[3] {} } { 0.000ns 0.000ns 1.308ns 2.668ns 0.877ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.699 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|CC[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.699 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|CC[4] {} } { 0.000ns 0.000ns 1.308ns 0.615ns } { 0.000ns 1.140ns 0.970ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.802 ns - Shortest register register " "Info: - Shortest register to register delay is 2.802 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsingl:inst\|CC\[4\] 1 REG LCFF_X8_Y9_N7 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y9_N7; Fanout = 7; REG Node = 'VGAsingl:inst\|CC\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGAsingl:inst|CC[4] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.147 ns) + CELL(0.206 ns) 1.353 ns VGAsingl:inst\|Equal4~41 2 COMB LCCOMB_X8_Y9_N10 3 " "Info: 2: + IC(1.147 ns) + CELL(0.206 ns) = 1.353 ns; Loc. = LCCOMB_X8_Y9_N10; Fanout = 3; COMB Node = 'VGAsingl:inst\|Equal4~41'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.353 ns" { VGAsingl:inst|CC[4] VGAsingl:inst|Equal4~41 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.206 ns) 1.924 ns VGAsingl:inst\|Equal4~42 3 COMB LCCOMB_X8_Y9_N16 4 " "Info: 3: + IC(0.365 ns) + CELL(0.206 ns) = 1.924 ns; Loc. = LCCOMB_X8_Y9_N16; Fanout = 4; COMB Node = 'VGAsingl:inst\|Equal4~42'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.571 ns" { VGAsingl:inst|Equal4~41 VGAsingl:inst|Equal4~42 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1837 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.370 ns) 2.694 ns VGAsingl:inst\|CC~200 4 COMB LCCOMB_X8_Y9_N4 1 " "Info: 4: + IC(0.400 ns) + CELL(0.370 ns) = 2.694 ns; Loc. = LCCOMB_X8_Y9_N4; Fanout = 1; COMB Node = 'VGAsingl:inst\|CC~200'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.770 ns" { VGAsingl:inst|Equal4~42 VGAsingl:inst|CC~200 } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.802 ns VGAsingl:inst\|CC\[3\] 5 REG LCFF_X8_Y9_N5 7 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 2.802 ns; Loc. = LCFF_X8_Y9_N5; Fanout = 7; REG Node = 'VGAsingl:inst\|CC\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { VGAsingl:inst|CC~200 VGAsingl:inst|CC[3] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 31.76 % ) " "Info: Total cell delay = 0.890 ns ( 31.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.912 ns ( 68.24 % ) " "Info: Total interconnect delay = 1.912 ns ( 68.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.802 ns" { VGAsingl:inst|CC[4] VGAsingl:inst|Equal4~41 VGAsingl:inst|Equal4~42 VGAsingl:inst|CC~200 VGAsingl:inst|CC[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.802 ns" { VGAsingl:inst|CC[4] {} VGAsingl:inst|Equal4~41 {} VGAsingl:inst|Equal4~42 {} VGAsingl:inst|CC~200 {} VGAsingl:inst|CC[3] {} } { 0.000ns 1.147ns 0.365ns 0.400ns 0.000ns } { 0.000ns 0.206ns 0.206ns 0.370ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.629 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.629 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|FS[5]~clkctrl {} VGAsingl:inst|CC[3] {} } { 0.000ns 0.000ns 1.308ns 2.668ns 0.877ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.699 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|CC[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.699 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|CC[4] {} } { 0.000ns 0.000ns 1.308ns 0.615ns } { 0.000ns 1.140ns 0.970ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.802 ns" { VGAsingl:inst|CC[4] VGAsingl:inst|Equal4~41 VGAsingl:inst|Equal4~42 VGAsingl:inst|CC~200 VGAsingl:inst|CC[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.802 ns" { VGAsingl:inst|CC[4] {} VGAsingl:inst|Equal4~41 {} VGAsingl:inst|Equal4~42 {} VGAsingl:inst|CC~200 {} VGAsingl:inst|CC[3] {} } { 0.000ns 1.147ns 0.365ns 0.400ns 0.000ns } { 0.000ns 0.206ns 0.206ns 0.370ns 0.108ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}