📄 vga.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 128 -48 120 144 "clk" "" } } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "reset " "Info: Assuming node \"reset\" is an undefined clock" { } { { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 144 -48 120 160 "reset" "" } } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "reset" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "VGAsingl:inst\|FS\[5\] " "Info: Detected ripple clock \"VGAsingl:inst\|FS\[5\]\" as buffer" { } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 10 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGAsingl:inst\|FS\[5\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "VGAsingl:inst\|CC\[4\] " "Info: Detected ripple clock \"VGAsingl:inst\|CC\[4\]\" as buffer" { } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "VGAsingl:inst\|CC\[4\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register VGAsingl:inst\|CC\[0\] register VGAsingl:inst\|CC\[4\] 175.75 MHz 5.69 ns Internal " "Info: Clock \"clk\" has Internal fmax of 175.75 MHz between source register \"VGAsingl:inst\|CC\[0\]\" and destination register \"VGAsingl:inst\|CC\[4\]\" (period= 5.69 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.496 ns + Longest register register " "Info: + Longest register to register delay is 2.496 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsingl:inst\|CC\[0\] 1 REG LCFF_X8_Y9_N23 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y9_N23; Fanout = 4; REG Node = 'VGAsingl:inst\|CC\[0\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGAsingl:inst|CC[0] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.456 ns) + CELL(0.596 ns) 1.052 ns VGAsingl:inst\|Add2~61 2 COMB LCCOMB_X8_Y9_N22 2 " "Info: 2: + IC(0.456 ns) + CELL(0.596 ns) = 1.052 ns; Loc. = LCCOMB_X8_Y9_N22; Fanout = 2; COMB Node = 'VGAsingl:inst\|Add2~61'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.052 ns" { VGAsingl:inst|CC[0] VGAsingl:inst|Add2~61 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.138 ns VGAsingl:inst\|Add2~63 3 COMB LCCOMB_X8_Y9_N24 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.138 ns; Loc. = LCCOMB_X8_Y9_N24; Fanout = 2; COMB Node = 'VGAsingl:inst\|Add2~63'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { VGAsingl:inst|Add2~61 VGAsingl:inst|Add2~63 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.224 ns VGAsingl:inst\|Add2~65 4 COMB LCCOMB_X8_Y9_N26 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.224 ns; Loc. = LCCOMB_X8_Y9_N26; Fanout = 2; COMB Node = 'VGAsingl:inst\|Add2~65'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { VGAsingl:inst|Add2~63 VGAsingl:inst|Add2~65 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.310 ns VGAsingl:inst\|Add2~67 5 COMB LCCOMB_X8_Y9_N28 1 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.310 ns; Loc. = LCCOMB_X8_Y9_N28; Fanout = 1; COMB Node = 'VGAsingl:inst\|Add2~67'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { VGAsingl:inst|Add2~65 VGAsingl:inst|Add2~67 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 1.816 ns VGAsingl:inst\|Add2~68 6 COMB LCCOMB_X8_Y9_N30 1 " "Info: 6: + IC(0.000 ns) + CELL(0.506 ns) = 1.816 ns; Loc. = LCCOMB_X8_Y9_N30; Fanout = 1; COMB Node = 'VGAsingl:inst\|Add2~68'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { VGAsingl:inst|Add2~67 VGAsingl:inst|Add2~68 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.366 ns) + CELL(0.206 ns) 2.388 ns VGAsingl:inst\|CC~201 7 COMB LCCOMB_X8_Y9_N6 1 " "Info: 7: + IC(0.366 ns) + CELL(0.206 ns) = 2.388 ns; Loc. = LCCOMB_X8_Y9_N6; Fanout = 1; COMB Node = 'VGAsingl:inst\|CC~201'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.572 ns" { VGAsingl:inst|Add2~68 VGAsingl:inst|CC~201 } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 2.496 ns VGAsingl:inst\|CC\[4\] 8 REG LCFF_X8_Y9_N7 7 " "Info: 8: + IC(0.000 ns) + CELL(0.108 ns) = 2.496 ns; Loc. = LCFF_X8_Y9_N7; Fanout = 7; REG Node = 'VGAsingl:inst\|CC\[4\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { VGAsingl:inst|CC~201 VGAsingl:inst|CC[4] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.674 ns ( 67.07 % ) " "Info: Total cell delay = 1.674 ns ( 67.07 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.822 ns ( 32.93 % ) " "Info: Total interconnect delay = 0.822 ns ( 32.93 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.496 ns" { VGAsingl:inst|CC[0] VGAsingl:inst|Add2~61 VGAsingl:inst|Add2~63 VGAsingl:inst|Add2~65 VGAsingl:inst|Add2~67 VGAsingl:inst|Add2~68 VGAsingl:inst|CC~201 VGAsingl:inst|CC[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.496 ns" { VGAsingl:inst|CC[0] {} VGAsingl:inst|Add2~61 {} VGAsingl:inst|Add2~63 {} VGAsingl:inst|Add2~65 {} VGAsingl:inst|Add2~67 {} VGAsingl:inst|Add2~68 {} VGAsingl:inst|CC~201 {} VGAsingl:inst|CC[4] {} } { 0.000ns 0.456ns 0.000ns 0.000ns 0.000ns 0.000ns 0.366ns 0.000ns } { 0.000ns 0.596ns 0.086ns 0.086ns 0.086ns 0.506ns 0.206ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.930 ns - Smallest " "Info: - Smallest clock skew is -2.930 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 4.699 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 4.699 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 128 -48 120 144 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.308 ns) + CELL(0.970 ns) 3.418 ns VGAsingl:inst\|FS\[5\] 2 REG LCFF_X7_Y9_N15 4 " "Info: 2: + IC(1.308 ns) + CELL(0.970 ns) = 3.418 ns; Loc. = LCFF_X7_Y9_N15; Fanout = 4; REG Node = 'VGAsingl:inst\|FS\[5\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.278 ns" { clk VGAsingl:inst|FS[5] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.615 ns) + CELL(0.666 ns) 4.699 ns VGAsingl:inst\|CC\[4\] 3 REG LCFF_X8_Y9_N7 7 " "Info: 3: + IC(0.615 ns) + CELL(0.666 ns) = 4.699 ns; Loc. = LCFF_X8_Y9_N7; Fanout = 7; REG Node = 'VGAsingl:inst\|CC\[4\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.281 ns" { VGAsingl:inst|FS[5] VGAsingl:inst|CC[4] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 59.08 % ) " "Info: Total cell delay = 2.776 ns ( 59.08 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.923 ns ( 40.92 % ) " "Info: Total interconnect delay = 1.923 ns ( 40.92 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.699 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|CC[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.699 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|CC[4] {} } { 0.000ns 0.000ns 1.308ns 0.615ns } { 0.000ns 1.140ns 0.970ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.629 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.629 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 128 -48 120 144 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.308 ns) + CELL(0.970 ns) 3.418 ns VGAsingl:inst\|FS\[5\] 2 REG LCFF_X7_Y9_N15 4 " "Info: 2: + IC(1.308 ns) + CELL(0.970 ns) = 3.418 ns; Loc. = LCFF_X7_Y9_N15; Fanout = 4; REG Node = 'VGAsingl:inst\|FS\[5\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.278 ns" { clk VGAsingl:inst|FS[5] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.668 ns) + CELL(0.000 ns) 6.086 ns VGAsingl:inst\|FS\[5\]~clkctrl 3 COMB CLKCTRL_G6 4 " "Info: 3: + IC(2.668 ns) + CELL(0.000 ns) = 6.086 ns; Loc. = CLKCTRL_G6; Fanout = 4; COMB Node = 'VGAsingl:inst\|FS\[5\]~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.668 ns" { VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.877 ns) + CELL(0.666 ns) 7.629 ns VGAsingl:inst\|CC\[0\] 4 REG LCFF_X8_Y9_N23 4 " "Info: 4: + IC(0.877 ns) + CELL(0.666 ns) = 7.629 ns; Loc. = LCFF_X8_Y9_N23; Fanout = 4; REG Node = 'VGAsingl:inst\|CC\[0\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.543 ns" { VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[0] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 36.39 % ) " "Info: Total cell delay = 2.776 ns ( 36.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.853 ns ( 63.61 % ) " "Info: Total interconnect delay = 4.853 ns ( 63.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.629 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.629 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|FS[5]~clkctrl {} VGAsingl:inst|CC[0] {} } { 0.000ns 0.000ns 1.308ns 2.668ns 0.877ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.699 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|CC[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.699 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|CC[4] {} } { 0.000ns 0.000ns 1.308ns 0.615ns } { 0.000ns 1.140ns 0.970ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.629 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.629 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|FS[5]~clkctrl {} VGAsingl:inst|CC[0] {} } { 0.000ns 0.000ns 1.308ns 2.668ns 0.877ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.496 ns" { VGAsingl:inst|CC[0] VGAsingl:inst|Add2~61 VGAsingl:inst|Add2~63 VGAsingl:inst|Add2~65 VGAsingl:inst|Add2~67 VGAsingl:inst|Add2~68 VGAsingl:inst|CC~201 VGAsingl:inst|CC[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.496 ns" { VGAsingl:inst|CC[0] {} VGAsingl:inst|Add2~61 {} VGAsingl:inst|Add2~63 {} VGAsingl:inst|Add2~65 {} VGAsingl:inst|Add2~67 {} VGAsingl:inst|Add2~68 {} VGAsingl:inst|CC~201 {} VGAsingl:inst|CC[4] {} } { 0.000ns 0.456ns 0.000ns 0.000ns 0.000ns 0.000ns 0.366ns 0.000ns } { 0.000ns 0.596ns 0.086ns 0.086ns 0.086ns 0.506ns 0.206ns 0.108ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.699 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|CC[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.699 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|CC[4] {} } { 0.000ns 0.000ns 1.308ns 0.615ns } { 0.000ns 1.140ns 0.970ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.629 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|FS[5]~clkctrl VGAsingl:inst|CC[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.629 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|FS[5]~clkctrl {} VGAsingl:inst|CC[0] {} } { 0.000ns 0.000ns 1.308ns 2.668ns 0.877ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
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