prev_cmp_vga.tan.qmsg

VGA显示的例子（VHDL语言）

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "reset register register VGAsingl:inst\|MMD\[0\] VGAsingl:inst\|MMD\[1\] 340.02 MHz Internal " "Info: Clock \"reset\" Internal fmax is restricted to 340.02 MHz between source register \"VGAsingl:inst\|MMD\[0\]\" and destination register \"VGAsingl:inst\|MMD\[1\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.941 ns " "Info: fmax restricted to clock pin edge rate 2.941 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.788 ns + Longest register register " "Info: + Longest register to register delay is 0.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsingl:inst\|MMD\[0\] 1 REG LCFF_X31_Y17_N7 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y17_N7; Fanout = 9; REG Node = 'VGAsingl:inst\|MMD\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGAsingl:inst|MMD[0] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.474 ns) + CELL(0.206 ns) 0.680 ns VGAsingl:inst\|MMD~43 2 COMB LCCOMB_X31_Y17_N2 1 " "Info: 2: + IC(0.474 ns) + CELL(0.206 ns) = 0.680 ns; Loc. = LCCOMB_X31_Y17_N2; Fanout = 1; COMB Node = 'VGAsingl:inst\|MMD~43'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.680 ns" { VGAsingl:inst|MMD[0] VGAsingl:inst|MMD~43 } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.788 ns VGAsingl:inst\|MMD\[1\] 3 REG LCFF_X31_Y17_N3 5 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.788 ns; Loc. = LCFF_X31_Y17_N3; Fanout = 5; REG Node = 'VGAsingl:inst\|MMD\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { VGAsingl:inst|MMD~43 VGAsingl:inst|MMD[1] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.314 ns ( 39.85 % ) " "Info: Total cell delay = 0.314 ns ( 39.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.474 ns ( 60.15 % ) " "Info: Total interconnect delay = 0.474 ns ( 60.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.788 ns" { VGAsingl:inst|MMD[0] VGAsingl:inst|MMD~43 VGAsingl:inst|MMD[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.788 ns" { VGAsingl:inst|MMD[0] {} VGAsingl:inst|MMD~43 {} VGAsingl:inst|MMD[1] {} } { 0.000ns 0.474ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "reset destination 2.864 ns + Shortest register " "Info: + Shortest clock path from clock \"reset\" to destination register is 2.864 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns reset 1 CLK PIN_24 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 4; CLK Node = 'reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 144 -48 120 160 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns reset~clkctrl 2 COMB CLKCTRL_G1 2 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 2; COMB Node = 'reset~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { reset reset~clkctrl } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 144 -48 120 160 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.666 ns) 2.864 ns VGAsingl:inst\|MMD\[1\] 3 REG LCFF_X31_Y17_N3 5 " "Info: 3: + IC(0.929 ns) + CELL(0.666 ns) = 2.864 ns; Loc. = LCFF_X31_Y17_N3; Fanout = 5; REG Node = 'VGAsingl:inst\|MMD\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.595 ns" { reset~clkctrl VGAsingl:inst|MMD[1] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.796 ns ( 62.71 % ) " "Info: Total cell delay = 1.796 ns ( 62.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.068 ns ( 37.29 % ) " "Info: Total interconnect delay = 1.068 ns ( 37.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { reset reset~clkctrl VGAsingl:inst|MMD[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { reset {} reset~combout {} reset~clkctrl {} VGAsingl:inst|MMD[1] {} } { 0.000ns 0.000ns 0.139ns 0.929ns } { 0.000ns 1.130ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "reset source 2.864 ns - Longest register " "Info: - Longest clock path from clock \"reset\" to source register is 2.864 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns reset 1 CLK PIN_24 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 4; CLK Node = 'reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 144 -48 120 160 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.269 ns reset~clkctrl 2 COMB CLKCTRL_G1 2 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.269 ns; Loc. = CLKCTRL_G1; Fanout = 2; COMB Node = 'reset~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { reset reset~clkctrl } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 144 -48 120 160 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.929 ns) + CELL(0.666 ns) 2.864 ns VGAsingl:inst\|MMD\[0\] 3 REG LCFF_X31_Y17_N7 9 " "Info: 3: + IC(0.929 ns) + CELL(0.666 ns) = 2.864 ns; Loc. = LCFF_X31_Y17_N7; Fanout = 9; REG Node = 'VGAsingl:inst\|MMD\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.595 ns" { reset~clkctrl VGAsingl:inst|MMD[0] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.796 ns ( 62.71 % ) " "Info: Total cell delay = 1.796 ns ( 62.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.068 ns ( 37.29 % ) " "Info: Total interconnect delay = 1.068 ns ( 37.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { reset reset~clkctrl VGAsingl:inst|MMD[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { reset {} reset~combout {} reset~clkctrl {} VGAsingl:inst|MMD[0] {} } { 0.000ns 0.000ns 0.139ns 0.929ns } { 0.000ns 1.130ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { reset reset~clkctrl VGAsingl:inst|MMD[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { reset {} reset~combout {} reset~clkctrl {} VGAsingl:inst|MMD[1] {} } { 0.000ns 0.000ns 0.139ns 0.929ns } { 0.000ns 1.130ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { reset reset~clkctrl VGAsingl:inst|MMD[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { reset {} reset~combout {} reset~clkctrl {} VGAsingl:inst|MMD[0] {} } { 0.000ns 0.000ns 0.139ns 0.929ns } { 0.000ns 1.130ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.788 ns" { VGAsingl:inst|MMD[0] VGAsingl:inst|MMD~43 VGAsingl:inst|MMD[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.788 ns" { VGAsingl:inst|MMD[0] {} VGAsingl:inst|MMD~43 {} VGAsingl:inst|MMD[1] {} } { 0.000ns 0.474ns 0.000ns } { 0.000ns 0.206ns 0.108ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { reset reset~clkctrl VGAsingl:inst|MMD[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { reset {} reset~combout {} reset~clkctrl {} VGAsingl:inst|MMD[1] {} } { 0.000ns 0.000ns 0.139ns 0.929ns } { 0.000ns 1.130ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.864 ns" { reset reset~clkctrl VGAsingl:inst|MMD[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.864 ns" { reset {} reset~combout {} reset~clkctrl {} VGAsingl:inst|MMD[0] {} } { 0.000ns 0.000ns 0.139ns 0.929ns } { 0.000ns 1.130ns 0.000ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGAsingl:inst|MMD[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { VGAsingl:inst|MMD[1] {} } {  } {  } "" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 23 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk b VGAsingl:inst\|LL\[5\] 20.961 ns register " "Info: tco from clock \"clk\" to destination pin \"b\" through register \"VGAsingl:inst\|LL\[5\]\" is 20.961 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.907 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.907 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 128 -48 120 144 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.448 ns) + CELL(0.970 ns) 3.558 ns VGAsingl:inst\|FS\[5\] 2 REG LCFF_X12_Y10_N7 4 " "Info: 2: + IC(1.448 ns) + CELL(0.970 ns) = 3.558 ns; Loc. = LCFF_X12_Y10_N7; Fanout = 4; REG Node = 'VGAsingl:inst\|FS\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.418 ns" { clk VGAsingl:inst|FS[5] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.021 ns) + CELL(0.970 ns) 6.549 ns VGAsingl:inst\|CC\[4\] 3 REG LCFF_X33_Y10_N7 7 " "Info: 3: + IC(2.021 ns) + CELL(0.970 ns) = 6.549 ns; Loc. = LCFF_X33_Y10_N7; Fanout = 7; REG Node = 'VGAsingl:inst\|CC\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.991 ns" { VGAsingl:inst|FS[5] VGAsingl:inst|CC[4] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.764 ns) + CELL(0.000 ns) 7.313 ns VGAsingl:inst\|CC\[4\]~clkctrl 4 COMB CLKCTRL_G6 9 " "Info: 4: + IC(0.764 ns) + CELL(0.000 ns) = 7.313 ns; Loc. = CLKCTRL_G6; Fanout = 9; COMB Node = 'VGAsingl:inst\|CC\[4\]~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.764 ns" { VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.928 ns) + CELL(0.666 ns) 8.907 ns VGAsingl:inst\|LL\[5\] 5 REG LCFF_X29_Y17_N1 8 " "Info: 5: + IC(0.928 ns) + CELL(0.666 ns) = 8.907 ns; Loc. = LCFF_X29_Y17_N1; Fanout = 8; REG Node = 'VGAsingl:inst\|LL\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.594 ns" { VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[5] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 42.06 % ) " "Info: Total cell delay = 3.746 ns ( 42.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.161 ns ( 57.94 % ) " "Info: Total interconnect delay = 5.161 ns ( 57.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.907 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.907 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|CC[4] {} VGAsingl:inst|CC[4]~clkctrl {} VGAsingl:inst|LL[5] {} } { 0.000ns 0.000ns 1.448ns 2.021ns 0.764ns 0.928ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 53 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.750 ns + Longest register pin " "Info: + Longest register to pin delay is 11.750 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns VGAsingl:inst\|LL\[5\] 1 REG LCFF_X29_Y17_N1 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y17_N1; Fanout = 8; REG Node = 'VGAsingl:inst\|LL\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { VGAsingl:inst|LL[5] } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.126 ns) + CELL(0.651 ns) 1.777 ns VGAsingl:inst\|LessThan14~85 2 COMB LCCOMB_X31_Y17_N14 2 " "Info: 2: + IC(1.126 ns) + CELL(0.651 ns) = 1.777 ns; Loc. = LCCOMB_X31_Y17_N14; Fanout = 2; COMB Node = 'VGAsingl:inst\|LessThan14~85'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.777 ns" { VGAsingl:inst|LL[5] VGAsingl:inst|LessThan14~85 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.658 ns) + CELL(0.650 ns) 3.085 ns VGAsingl:inst\|B~1374 3 COMB LCCOMB_X31_Y17_N4 1 " "Info: 3: + IC(0.658 ns) + CELL(0.650 ns) = 3.085 ns; Loc. = LCCOMB_X31_Y17_N4; Fanout = 1; COMB Node = 'VGAsingl:inst\|B~1374'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.308 ns" { VGAsingl:inst|LessThan14~85 VGAsingl:inst|B~1374 } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.667 ns) + CELL(0.370 ns) 4.122 ns VGAsingl:inst\|B~1378 4 COMB LCCOMB_X31_Y17_N20 1 " "Info: 4: + IC(0.667 ns) + CELL(0.370 ns) = 4.122 ns; Loc. = LCCOMB_X31_Y17_N20; Fanout = 1; COMB Node = 'VGAsingl:inst\|B~1378'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.037 ns" { VGAsingl:inst|B~1374 VGAsingl:inst|B~1378 } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.391 ns) + CELL(0.614 ns) 5.127 ns VGAsingl:inst\|B~1382 5 COMB LCCOMB_X31_Y17_N22 1 " "Info: 5: + IC(0.391 ns) + CELL(0.614 ns) = 5.127 ns; Loc. = LCCOMB_X31_Y17_N22; Fanout = 1; COMB Node = 'VGAsingl:inst\|B~1382'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.005 ns" { VGAsingl:inst|B~1378 VGAsingl:inst|B~1382 } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.507 ns) + CELL(3.116 ns) 11.750 ns b 6 PIN PIN_5 0 " "Info: 6: + IC(3.507 ns) + CELL(3.116 ns) = 11.750 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'b'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.623 ns" { VGAsingl:inst|B~1382 b } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 192 472 648 208 "b" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.401 ns ( 45.97 % ) " "Info: Total cell delay = 5.401 ns ( 45.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.349 ns ( 54.03 % ) " "Info: Total interconnect delay = 6.349 ns ( 54.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.750 ns" { VGAsingl:inst|LL[5] VGAsingl:inst|LessThan14~85 VGAsingl:inst|B~1374 VGAsingl:inst|B~1378 VGAsingl:inst|B~1382 b } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.750 ns" { VGAsingl:inst|LL[5] {} VGAsingl:inst|LessThan14~85 {} VGAsingl:inst|B~1374 {} VGAsingl:inst|B~1378 {} VGAsingl:inst|B~1382 {} b {} } { 0.000ns 1.126ns 0.658ns 0.667ns 0.391ns 3.507ns } { 0.000ns 0.651ns 0.650ns 0.370ns 0.614ns 3.116ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.907 ns" { clk VGAsingl:inst|FS[5] VGAsingl:inst|CC[4] VGAsingl:inst|CC[4]~clkctrl VGAsingl:inst|LL[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.907 ns" { clk {} clk~combout {} VGAsingl:inst|FS[5] {} VGAsingl:inst|CC[4] {} VGAsingl:inst|CC[4]~clkctrl {} VGAsingl:inst|LL[5] {} } { 0.000ns 0.000ns 1.448ns 2.021ns 0.764ns 0.928ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.750 ns" { VGAsingl:inst|LL[5] VGAsingl:inst|LessThan14~85 VGAsingl:inst|B~1374 VGAsingl:inst|B~1378 VGAsingl:inst|B~1382 b } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.750 ns" { VGAsingl:inst|LL[5] {} VGAsingl:inst|LessThan14~85 {} VGAsingl:inst|B~1374 {} VGAsingl:inst|B~1378 {} VGAsingl:inst|B~1382 {} b {} } { 0.000ns 1.126ns 0.658ns 0.667ns 0.391ns 3.507ns } { 0.000ns 0.651ns 0.650ns 0.370ns 0.614ns 3.116ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "reset b 10.998 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"b\" is 10.998 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns reset 1 CLK PIN_24 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_24; Fanout = 4; CLK Node = 'reset'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 144 -48 120 160 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.656 ns) + CELL(0.589 ns) 4.375 ns VGAsingl:inst\|B~1382 2 COMB LCCOMB_X31_Y17_N22 1 " "Info: 2: + IC(2.656 ns) + CELL(0.589 ns) = 4.375 ns; Loc. = LCCOMB_X31_Y17_N22; Fanout = 1; COMB Node = 'VGAsingl:inst\|B~1382'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.245 ns" { reset VGAsingl:inst|B~1382 } "NODE_NAME" } } { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.507 ns) + CELL(3.116 ns) 10.998 ns b 3 PIN PIN_5 0 " "Info: 3: + IC(3.507 ns) + CELL(3.116 ns) = 10.998 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'b'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.623 ns" { VGAsingl:inst|B~1382 b } "NODE_NAME" } } { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 192 472 648 208 "b" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.835 ns ( 43.96 % ) " "Info: Total cell delay = 4.835 ns ( 43.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.163 ns ( 56.04 % ) " "Info: Total interconnect delay = 6.163 ns ( 56.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.998 ns" { reset VGAsingl:inst|B~1382 b } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.998 ns" { reset {} reset~combout {} VGAsingl:inst|B~1382 {} b {} } { 0.000ns 0.000ns 2.656ns 3.507ns } { 0.000ns 1.130ns 0.589ns 3.116ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}