📄 vga.map.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 12 19:47:44 2008 " "Info: Processing started: Thu Jun 12 19:47:44 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off VGA -c VGA " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off VGA -c VGA" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "VGA.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file VGA.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 VGA " "Info: Found entity 1: VGA" { } { { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "VGAsingl.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file VGAsingl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 VGAsingl-behav " "Info: Found design unit 1: VGAsingl-behav" { } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 7 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 VGAsingl " "Info: Found entity 1: VGAsingl" { } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 4 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "VGA " "Info: Elaborating entity \"VGA\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "VGA " "Warning: Processing legacy GDF or BDF entity \"VGA\" with Max+Plus II bus and instance naming rules" { } { { "VGA.bdf" "" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { } } } } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "VGAsingl VGAsingl:inst " "Info: Elaborating entity \"VGAsingl\" for hierarchy \"VGAsingl:inst\"" { } { { "VGA.bdf" "inst" { Schematic "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf" { { 104 296 392 232 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "GRBX VGAsingl.vhd(30) " "Warning (10492): VHDL Process Statement warning at VGAsingl.vhd(30): signal \"GRBX\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 30 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "GRBY VGAsingl.vhd(31) " "Warning (10492): VHDL Process Statement warning at VGAsingl.vhd(31): signal \"GRBY\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 31 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "GRBX VGAsingl.vhd(32) " "Warning (10492): VHDL Process Statement warning at VGAsingl.vhd(32): signal \"GRBX\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 32 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "GRBY VGAsingl.vhd(32) " "Warning (10492): VHDL Process Statement warning at VGAsingl.vhd(32): signal \"GRBY\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { { "VGAsingl.vhd" "" { Text "F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd" 32 0 0 } } } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "73 " "Info: Implemented 73 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Info: Implemented 5 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "66 " "Info: Implemented 66 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "163 " "Info: Allocated 163 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 12 19:47:54 2008 " "Info: Processing ended: Thu Jun 12 19:47:54 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
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