vga.tan.rpt

VGA显示的例子（VHDL语言）

        Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.224 ns; Loc. = LCCOMB_X8_Y9_N26; Fanout = 2; COMB Node = 'VGAsingl:inst|Add2~65'
        Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.310 ns; Loc. = LCCOMB_X8_Y9_N28; Fanout = 1; COMB Node = 'VGAsingl:inst|Add2~67'
        Info: 6: + IC(0.000 ns) + CELL(0.506 ns) = 1.816 ns; Loc. = LCCOMB_X8_Y9_N30; Fanout = 1; COMB Node = 'VGAsingl:inst|Add2~68'
        Info: 7: + IC(0.366 ns) + CELL(0.206 ns) = 2.388 ns; Loc. = LCCOMB_X8_Y9_N6; Fanout = 1; COMB Node = 'VGAsingl:inst|CC~201'
        Info: 8: + IC(0.000 ns) + CELL(0.108 ns) = 2.496 ns; Loc. = LCFF_X8_Y9_N7; Fanout = 7; REG Node = 'VGAsingl:inst|CC[4]'
        Info: Total cell delay = 1.674 ns ( 67.07 % )
        Info: Total interconnect delay = 0.822 ns ( 32.93 % )
    Info: - Smallest clock skew is -2.930 ns
        Info: + Shortest clock path from clock "clk" to destination register is 4.699 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'
            Info: 2: + IC(1.308 ns) + CELL(0.970 ns) = 3.418 ns; Loc. = LCFF_X7_Y9_N15; Fanout = 4; REG Node = 'VGAsingl:inst|FS[5]'
            Info: 3: + IC(0.615 ns) + CELL(0.666 ns) = 4.699 ns; Loc. = LCFF_X8_Y9_N7; Fanout = 7; REG Node = 'VGAsingl:inst|CC[4]'
            Info: Total cell delay = 2.776 ns ( 59.08 % )
            Info: Total interconnect delay = 1.923 ns ( 40.92 % )
        Info: - Longest clock path from clock "clk" to source register is 7.629 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'
            Info: 2: + IC(1.308 ns) + CELL(0.970 ns) = 3.418 ns; Loc. = LCFF_X7_Y9_N15; Fanout = 4; REG Node = 'VGAsingl:inst|FS[5]'
            Info: 3: + IC(2.668 ns) + CELL(0.000 ns) = 6.086 ns; Loc. = CLKCTRL_G6; Fanout = 4; COMB Node = 'VGAsingl:inst|FS[5]~clkctrl'
            Info: 4: + IC(0.877 ns) + CELL(0.666 ns) = 7.629 ns; Loc. = LCFF_X8_Y9_N23; Fanout = 4; REG Node = 'VGAsingl:inst|CC[0]'
            Info: Total cell delay = 2.776 ns ( 36.39 % )
            Info: Total interconnect delay = 4.853 ns ( 63.61 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: Clock "reset" Internal fmax is restricted to 360.1 MHz between source register "VGAsingl:inst|MMD[1]" and destination register "VGAsingl:inst|MMD[0]"
    Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.776 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y7_N1; Fanout = 5; REG Node = 'VGAsingl:inst|MMD[1]'
            Info: 2: + IC(0.466 ns) + CELL(0.202 ns) = 0.668 ns; Loc. = LCCOMB_X21_Y7_N6; Fanout = 1; COMB Node = 'VGAsingl:inst|MMD~42'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.776 ns; Loc. = LCFF_X21_Y7_N7; Fanout = 9; REG Node = 'VGAsingl:inst|MMD[0]'
            Info: Total cell delay = 0.310 ns ( 39.95 % )
            Info: Total interconnect delay = 0.466 ns ( 60.05 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "reset" to destination register is 4.085 ns
                Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_56; Fanout = 5; CLK Node = 'reset'
                Info: 2: + IC(2.435 ns) + CELL(0.666 ns) = 4.085 ns; Loc. = LCFF_X21_Y7_N7; Fanout = 9; REG Node = 'VGAsingl:inst|MMD[0]'
                Info: Total cell delay = 1.650 ns ( 40.39 % )
                Info: Total interconnect delay = 2.435 ns ( 59.61 % )
            Info: - Longest clock path from clock "reset" to source register is 4.085 ns
                Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_56; Fanout = 5; CLK Node = 'reset'
                Info: 2: + IC(2.435 ns) + CELL(0.666 ns) = 4.085 ns; Loc. = LCFF_X21_Y7_N1; Fanout = 5; REG Node = 'VGAsingl:inst|MMD[1]'
                Info: Total cell delay = 1.650 ns ( 40.39 % )
                Info: Total interconnect delay = 2.435 ns ( 59.61 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "VGAsingl:inst|CC[4]" and destination pin or register "VGAsingl:inst|CC[3]" for clock "clk" (Hold time is 130 ps)
    Info: + Largest clock skew is 2.930 ns
        Info: + Longest clock path from clock "clk" to destination register is 7.629 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'
            Info: 2: + IC(1.308 ns) + CELL(0.970 ns) = 3.418 ns; Loc. = LCFF_X7_Y9_N15; Fanout = 4; REG Node = 'VGAsingl:inst|FS[5]'
            Info: 3: + IC(2.668 ns) + CELL(0.000 ns) = 6.086 ns; Loc. = CLKCTRL_G6; Fanout = 4; COMB Node = 'VGAsingl:inst|FS[5]~clkctrl'
            Info: 4: + IC(0.877 ns) + CELL(0.666 ns) = 7.629 ns; Loc. = LCFF_X8_Y9_N5; Fanout = 7; REG Node = 'VGAsingl:inst|CC[3]'
            Info: Total cell delay = 2.776 ns ( 36.39 % )
            Info: Total interconnect delay = 4.853 ns ( 63.61 % )
        Info: - Shortest clock path from clock "clk" to source register is 4.699 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'
            Info: 2: + IC(1.308 ns) + CELL(0.970 ns) = 3.418 ns; Loc. = LCFF_X7_Y9_N15; Fanout = 4; REG Node = 'VGAsingl:inst|FS[5]'
            Info: 3: + IC(0.615 ns) + CELL(0.666 ns) = 4.699 ns; Loc. = LCFF_X8_Y9_N7; Fanout = 7; REG Node = 'VGAsingl:inst|CC[4]'
            Info: Total cell delay = 2.776 ns ( 59.08 % )
            Info: Total interconnect delay = 1.923 ns ( 40.92 % )
    Info: - Micro clock to output delay of source is 0.304 ns
    Info: - Shortest register to register delay is 2.802 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y9_N7; Fanout = 7; REG Node = 'VGAsingl:inst|CC[4]'
        Info: 2: + IC(1.147 ns) + CELL(0.206 ns) = 1.353 ns; Loc. = LCCOMB_X8_Y9_N10; Fanout = 3; COMB Node = 'VGAsingl:inst|Equal4~41'
        Info: 3: + IC(0.365 ns) + CELL(0.206 ns) = 1.924 ns; Loc. = LCCOMB_X8_Y9_N16; Fanout = 4; COMB Node = 'VGAsingl:inst|Equal4~42'
        Info: 4: + IC(0.400 ns) + CELL(0.370 ns) = 2.694 ns; Loc. = LCCOMB_X8_Y9_N4; Fanout = 1; COMB Node = 'VGAsingl:inst|CC~200'
        Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 2.802 ns; Loc. = LCFF_X8_Y9_N5; Fanout = 7; REG Node = 'VGAsingl:inst|CC[3]'
        Info: Total cell delay = 0.890 ns ( 31.76 % )
        Info: Total interconnect delay = 1.912 ns ( 68.24 % )
    Info: + Micro hold delay of destination is 0.306 ns
Info: tco from clock "clk" to destination pin "b" through register "VGAsingl:inst|LL[3]" is 19.653 ns
    Info: + Longest clock path from clock "clk" to source register is 8.041 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(1.308 ns) + CELL(0.970 ns) = 3.418 ns; Loc. = LCFF_X7_Y9_N15; Fanout = 4; REG Node = 'VGAsingl:inst|FS[5]'
        Info: 3: + IC(0.615 ns) + CELL(0.970 ns) = 5.003 ns; Loc. = LCFF_X8_Y9_N7; Fanout = 7; REG Node = 'VGAsingl:inst|CC[4]'
        Info: 4: + IC(1.516 ns) + CELL(0.000 ns) = 6.519 ns; Loc. = CLKCTRL_G0; Fanout = 9; COMB Node = 'VGAsingl:inst|CC[4]~clkctrl'
        Info: 5: + IC(0.856 ns) + CELL(0.666 ns) = 8.041 ns; Loc. = LCFF_X18_Y10_N11; Fanout = 8; REG Node = 'VGAsingl:inst|LL[3]'
        Info: Total cell delay = 3.746 ns ( 46.59 % )
        Info: Total interconnect delay = 4.295 ns ( 53.41 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 11.308 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y10_N11; Fanout = 8; REG Node = 'VGAsingl:inst|LL[3]'
        Info: 2: + IC(1.482 ns) + CELL(0.651 ns) = 2.133 ns; Loc. = LCCOMB_X18_Y7_N0; Fanout = 1; COMB Node = 'VGAsingl:inst|B~1372'
        Info: 3: + IC(1.094 ns) + CELL(0.370 ns) = 3.597 ns; Loc. = LCCOMB_X21_Y7_N10; Fanout = 1; COMB Node = 'VGAsingl:inst|B~1374'
        Info: 4: + IC(0.393 ns) + CELL(0.650 ns) = 4.640 ns; Loc. = LCCOMB_X21_Y7_N22; Fanout = 1; COMB Node = 'VGAsingl:inst|B~1378'
        Info: 5: + IC(0.362 ns) + CELL(0.623 ns) = 5.625 ns; Loc. = LCCOMB_X21_Y7_N2; Fanout = 1; COMB Node = 'VGAsingl:inst|B~1382'
        Info: 6: + IC(2.577 ns) + CELL(3.106 ns) = 11.308 ns; Loc. = PIN_114; Fanout = 0; PIN Node = 'b'
        Info: Total cell delay = 5.400 ns ( 47.75 % )
        Info: Total interconnect delay = 5.908 ns ( 52.25 % )
Info: Longest tpd from source pin "reset" to destination pin "r" is 15.428 ns
    Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_56; Fanout = 5; CLK Node = 'reset'
    Info: 2: + IC(6.928 ns) + CELL(0.370 ns) = 8.282 ns; Loc. = LCCOMB_X21_Y7_N4; Fanout = 1; COMB Node = 'VGAsingl:inst|R~546'
    Info: 3: + IC(1.027 ns) + CELL(0.616 ns) = 9.925 ns; Loc. = LCCOMB_X21_Y7_N20; Fanout = 1; COMB Node = 'VGAsingl:inst|R~547'
    Info: 4: + IC(2.417 ns) + CELL(3.086 ns) = 15.428 ns; Loc. = PIN_112; Fanout = 0; PIN Node = 'r'
    Info: Total cell delay = 5.056 ns ( 32.77 % )
    Info: Total interconnect delay = 10.372 ns ( 67.23 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Thu Jun 12 19:48:40 2008
    Info: Elapsed time: 00:00:03