vgasingl.vhd

VGA显示的例子（VHDL语言）

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity VGAsingl is
 PORT( CLK,MD:IN STD_LOGIC;HS,VS,R,G,B:OUT STD_LOGIC);
END VGAsingl;
ARCHITECTURE behav OF VGAsingl IS
  SIGNAL HS1,VS1,FCLK,CCLK:STD_LOGIC;
  SIGNAL MMD:STD_LOGIC_VECTOR(1 DOWNTO 0);
  SIGNAL FS :STD_LOGIC_VECTOR(5 DOWNTO 0);
  SIGNAL CC :STD_LOGIC_VECTOR(4 DOWNTO 0);
  SIGNAL LL :STD_LOGIC_VECTOR(8 DOWNTO 0);
  SIGNAL GRBX:STD_LOGIC_VECTOR(3 DOWNTO 1);
  SIGNAL GRBY:STD_LOGIC_VECTOR(3 DOWNTO 1);
  SIGNAL GRBP:STD_LOGIC_VECTOR(3 DOWNTO 1);
  SIGNAL GRB :STD_LOGIC_VECTOR(3 DOWNTO 1);
BEGIN
  GRB(2)<=(GRBP(2) XOR MD) AND HS1 AND VS1;
  GRB(3)<=(GRBP(3) XOR MD) AND HS1 AND VS1;
  GRB(1)<=(GRBP(1) XOR MD) AND HS1 AND VS1;
PROCESS(MD)
BEGIN
    IF MD'EVENT AND MD ='0' THEN 
       IF MMD="10" THEN MMD<="00";
         ELSE MMD<=MMD+1;END IF;
    END IF; 
END PROCESS;  
  PROCESS(MMD)
    BEGIN
      IF MMD="00" THEN GRBP<=GRBX;
       ELSIF MMD="01" THEN GRBP<=GRBY;
       ELSIF MMD="10" THEN GRBP<=GRBX XOR GRBY;
         ELSE GRBP<="000";END IF;
END PROCESS;
   PROCESS(CLK)
     BEGIN
       IF CLK'EVENT AND CLK='1' THEN
           IF FS=50 THEN FS<="000000";
              ELSE FS<=FS+1; END IF;
       END IF;
END PROCESS;
FCLK<=FS(5);
PROCESS(FCLK)
   BEGIN
     IF FCLK'EVENT AND FCLK='1' THEN
        IF CC=29 THEN CC<="00000";
           ELSE CC<=CC+1;END IF;
     END IF;
END PROCESS;
CCLK<=CC(4);
PROCESS(CCLK)
 BEGIN
     IF CCLK'EVENT AND CCLK='0' THEN
       IF LL=481 THEN LL<="000000000";
         ELSE LL<=LL+1; END IF;
     END IF;
END PROCESS;
PROCESS(CC,LL)
BEGIN
  IF CC>23 THEN HS1<='0';
      ELSE HS1<='1';END IF;
  IF LL>479 THEN VS1<='0';
      ELSE VS1<='1';END IF;
END PROCESS;
PROCESS(CC,LL)
 BEGIN
   IF CC<3 THEN GRBX<="111";
    ELSIF CC<6  THEN GRBX<="110";
    ELSIF CC<9  THEN GRBX<="101";
    ELSIF CC<12 THEN GRBX<="100";
    ELSIF CC<15  THEN GRBX<="011";
    ELSIF CC<18  THEN GRBX<="010";
    ELSIF CC<21  THEN GRBX<="001";
     ELSE GRBX<="000" ; END IF;
        IF LL<60  THEN GRBY<="111";
     ELSIF LL<120 THEN GRBY<="110";
     ELSIF LL<180 THEN GRBY<="101";
     ELSIF LL<240 THEN GRBY<="100";
     ELSIF LL<300 THEN GRBY<="011";
     ELSIF LL<360 THEN GRBY<="010";
     ELSIF LL<420 THEN GRBY<="001";
     ELSE GRBY<="000"; END IF;
   END PROCESS;
   HS<=HS1;VS<=VS1;R<=GRB(2);G<=GRB(3);B<=GRB(1);
END behav;