vga.map.rpt

VGA显示的例子（VHDL语言）

; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Maximum Number of M4K/M9K Memory Blocks                                        ; Unlimited          ; Unlimited          ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                       ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                       ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------+
; VGA.bdf                          ; yes             ; User Block Diagram/Schematic File  ; F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGA.bdf      ;
; VGAsingl.vhd                     ; yes             ; User VHDL File                     ; F:/DEMO_FPGA/EP2C8-V5/VHDLProgram/VGA/VGAsingl.vhd ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------+


+-------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                       ;
+---------------------------------------------+---------------------+
; Resource                                    ; Usage               ;
+---------------------------------------------+---------------------+
; Estimated Total logic elements              ; 66                  ;
;                                             ;                     ;
; Total combinational functions               ; 66                  ;
; Logic element usage by number of LUT inputs ;                     ;
;     -- 4 input functions                    ; 33                  ;
;     -- 3 input functions                    ; 3                   ;
;     -- <=2 input functions                  ; 30                  ;
;                                             ;                     ;
; Logic elements by mode                      ;                     ;
;     -- normal mode                          ; 49                  ;
;     -- arithmetic mode                      ; 17                  ;
;                                             ;                     ;
; Total registers                             ; 22                  ;
;     -- Dedicated logic registers            ; 22                  ;
;     -- I/O registers                        ; 0                   ;
;                                             ;                     ;
; I/O pins                                    ; 7                   ;
; Maximum fan-out node                        ; VGAsingl:inst|CC[4] ;
; Maximum fan-out                             ; 15                  ;
; Total fan-out                               ; 247                 ;
; Average fan-out                             ; 2.60                ;
+---------------------------------------------+---------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |VGA                       ; 66 (0)            ; 22 (0)       ; 0           ; 0            ; 0       ; 0         ; 7    ; 0            ; |VGA                ; work         ;
;    |VGAsingl:inst|         ; 66 (66)           ; 22 (22)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |VGA|VGAsingl:inst  ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 22    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Thu Jun 12 19:47:44 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off VGA -c VGA
Info: Found 1 design units, including 1 entities, in source file VGA.bdf
    Info: Found entity 1: VGA
Info: Found 2 design units, including 1 entities, in source file VGAsingl.vhd
    Info: Found design unit 1: VGAsingl-behav
    Info: Found entity 1: VGAsingl
Info: Elaborating entity "VGA" for the top level hierarchy
Warning: Processing legacy GDF or BDF entity "VGA" with Max+Plus II bus and instance naming rules
Info: Elaborating entity "VGAsingl" for hierarchy "VGAsingl:inst"
Warning (10492): VHDL Process Statement warning at VGAsingl.vhd(30): signal "GRBX" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at VGAsingl.vhd(31): signal "GRBY" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at VGAsingl.vhd(32): signal "GRBX" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at VGAsingl.vhd(32): signal "GRBY" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Implemented 73 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 5 output pins
    Info: Implemented 66 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Allocated 163 megabytes of memory during processing
    Info: Processing ended: Thu Jun 12 19:47:54 2008
    Info: Elapsed time: 00:00:10