yyq.vhd

d 触发器 简单的d触发器

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--
-- Title       : yyq
-- Design      : dchufa
-- Author      : king
-- Company     : king
--
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--
-- File        : yyq.vhd
-- Generated   : Tue Dec 11 18:59:03 2007
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description : 
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {yyq} architecture {yyq}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;



entity yyq is
	 port(
		 a : in STD_LOGIC;
		 clk : in STD_LOGIC;
		 b : out STD_LOGIC
	     );
end yyq;

--}} End of automatically maintained section

architecture yyq of yyq is
component tt
		 port(
		 d : in STD_LOGIC;
		 clk : in STD_LOGIC;
		 q : out STD_LOGIC
	     );
end component; 

signal z:std_logic_vector(0 to 4);
  begin
z(0)<=a;
 b<=z(4);
dff1:tt port map (z(0),clk,z(1));
dff2:tt port map (z(1),clk,z(2));
dff3:tt port map (z(2),clk,z(3));
dff4:tt port map (z(3),clk,z(4));
	
	 -- enter your statements here --

end yyq;