📄 tt.vhd
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---------------------------------------------------------------------------------------------------
--
-- Title : tt
-- Design : dchufa
-- Author : king
-- Company : king
--
---------------------------------------------------------------------------------------------------
--
-- File : tt.vhd
-- Generated : Tue Dec 11 19:27:47 2007
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------
--
-- Description :
--
---------------------------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {tt} architecture {tt}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity tt is
port(
d : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC
);
end tt;
--}} End of automatically maintained section
architecture tt of tt is
begin
process(clk,d)
begin
if clk'event and clk='1' then
q<=d;
end if;
end process;
-- enter your statements here --
end tt;
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