📄 1dchufa.mgf
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(_model . dcf 1 -1
)
)
I 000043 55 596 1197372505297 yy(_unit VHDL (yy 0 30 (yy 0 38 ))
(_version v30)
(_time 1197372505296 2007.12.11 19:28:25)
(_source (\./src/yy.vhd\))
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(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
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)
I 000043 55 906 1197372505313 tt(_unit VHDL (tt 0 30 (tt 0 40 ))
(_version v30)
(_time 1197372505312 2007.12.11 19:28:25)
(_source (\./src/tt.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1197372505312)
(_use )
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(_object
(_port (_internal d ~extieee.std_logic_1164.std_logic 0 32 (_entity (_in ))))
(_port (_internal clk ~extieee.std_logic_1164.std_logic 0 33 (_entity (_in ))))
(_port (_internal q ~extieee.std_logic_1164.std_logic 0 34 (_entity (_out ))))
(_process
(line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
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(_subprogram
(_external resolved (ieee std_logic_1164 0))
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(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
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(_model . tt 1 -1
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I 000044 55 675 1197372553657 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
(_version v30)
(_time 1197372553656 2007.12.11 19:29:13)
(_source (\./src/dcf.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
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(_time 1197370345640)
(_use )
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(_object
(_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
(_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
(_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
(_process
(line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
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(_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
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(_model . dcf 1 -1
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I 000043 55 596 1197372553735 yy(_unit VHDL (yy 0 30 (yy 0 38 ))
(_version v30)
(_time 1197372553734 2007.12.11 19:29:13)
(_source (\./src/yy.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1197372505296)
(_use )
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(_object
(_port (_internal a ~extieee.std_logic_1164.std_logic 0 32 (_entity (_in ))))
(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
)
)
I 000043 55 906 1197372553751 tt(_unit VHDL (tt 0 30 (tt 0 40 ))
(_version v30)
(_time 1197372553750 2007.12.11 19:29:13)
(_source (\./src/tt.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1197372505312)
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(_object
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(_port (_internal q ~extieee.std_logic_1164.std_logic 0 34 (_entity (_out ))))
(_process
(line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
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(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
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(_model . tt 1 -1
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I 000044 55 675 1197372561000 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
(_version v30)
(_time 1197372561000 2007.12.11 19:29:21)
(_source (\./src/dcf.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1197370345640)
(_use )
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(_object
(_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
(_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
(_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
(_process
(line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
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(_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
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(_model . dcf 1 -1
)
)
I 000043 55 596 1197372561109 yy(_unit VHDL (yy 0 30 (yy 0 38 ))
(_version v30)
(_time 1197372561109 2007.12.11 19:29:21)
(_source (\./src/yy.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1197372505296)
(_use )
)
(_object
(_port (_internal a ~extieee.std_logic_1164.std_logic 0 32 (_entity (_in ))))
(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
)
)
I 000043 55 906 1197372561114 tt(_unit VHDL (tt 0 30 (tt 0 40 ))
(_version v30)
(_time 1197372561110 2007.12.11 19:29:21)
(_source (\./src/tt.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1197372505312)
(_use )
)
(_object
(_port (_internal d ~extieee.std_logic_1164.std_logic 0 32 (_entity (_in ))))
(_port (_internal clk ~extieee.std_logic_1164.std_logic 0 33 (_entity (_in ))))
(_port (_internal q ~extieee.std_logic_1164.std_logic 0 34 (_entity (_out ))))
(_process
(line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
)
(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
)
(_model . tt 1 -1
)
)
V 000044 55 675 1197372590140 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
(_version v30)
(_time 1197372590140 2007.12.11 19:29:50)
(_source (\./src/dcf.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1197370345640)
(_use )
)
(_object
(_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
(_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
(_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
(_process
(line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
)
(_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
)
(_model . dcf 1 -1
)
)
V 000044 55 2329 1197372590204 yyq(_unit VHDL (yyq 0 30 (yyq 0 40 ))
(_version v30)
(_time 1197372590203 2007.12.11 19:29:50)
(_source (\./src/yyq.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1197371216296)
(_use )
)
(_component
(tt
(_object
(_port (_internal d ~extieee.std_logic_1164.std_logic 0 43 (_entity (_in ))))
(_port (_internal clk ~extieee.std_logic_1164.std_logic 0 44 (_entity (_in ))))
(_port (_internal q ~extieee.std_logic_1164.std_logic 0 45 (_entity (_out ))))
)
)
)
(_instantiation dff1 0 53 (_component tt )
(_port
((d)(z(0)))
((clk)(clk))
((q)(z(1)))
)
(_use (_entity . tt)
)
)
(_instantiation dff2 0 54 (_component tt )
(_port
((d)(z(1)))
((clk)(clk))
((q)(z(2)))
)
(_use (_entity . tt)
)
)
(_instantiation dff3 0 55 (_component tt )
(_port
((d)(z(2)))
((clk)(clk))
((q)(z(3)))
)
(_use (_entity . tt)
)
)
(_instantiation dff4 0 56 (_component tt )
(_port
((d)(z(3)))
((clk)(clk))
((q)(z(4)))
)
(_use (_entity . tt)
)
)
(_object
(_port (_internal a ~extieee.std_logic_1164.std_logic 0 32 (_entity (_in ))))
(_port (_internal clk ~extieee.std_logic_1164.std_logic 0 33 (_entity (_in ))))
(_port (_internal b ~extieee.std_logic_1164.std_logic 0 34 (_entity (_out ))))
(_type (_internal ~std_logic_vector{0~to~4}~13 0 49 (_array ~extieee.std_logic_1164.std_logic ((_to (i 0)(i 4))))))
(_signal (_internal z ~std_logic_vector{0~to~4}~13 0 49 (_architecture (_uni ))))
(_process
(line__51(_architecture 0 0 51 (_assignment (_simple)(_alias((z(0))(a)))(_target(3(0)))(_sensitivity(0)))))
(line__52(_architecture 1 0 52 (_assignment (_simple)(_alias((b)(z(4))))(_target(2))(_sensitivity(3(4))))))
)
(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
(_type (_external ~extieee.std_logic_1164.std_logic_vector (ieee std_logic_1164 std_logic_vector)))
)
(_model . yyq 2 -1
)
)
V 000043 55 596 1197372590266 yy(_unit VHDL (yy 0 30 (yy 0 38 ))
(_version v30)
(_time 1197372590265 2007.12.11 19:29:50)
(_source (\./src/yy.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1197372505296)
(_use )
)
(_object
(_port (_internal a ~extieee.std_logic_1164.std_logic 0 32 (_entity (_in ))))
(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
)
)
V 000043 55 906 1197372590281 tt(_unit VHDL (tt 0 30 (tt 0 40 ))
(_version v30)
(_time 1197372590281 2007.12.11 19:29:50)
(_source (\./src/tt.vhd\))
(_use (std(standard))(ieee(std_logic_1164)))
(_entity
(_time 1197372505312)
(_use )
)
(_object
(_port (_internal d ~extieee.std_logic_1164.std_logic 0 32 (_entity (_in ))))
(_port (_internal clk ~extieee.std_logic_1164.std_logic 0 33 (_entity (_in ))))
(_port (_internal q ~extieee.std_logic_1164.std_logic 0 34 (_entity (_out ))))
(_process
(line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
)
(_subprogram
(_external resolved (ieee std_logic_1164 0))
)
(_type (_external ~extieee.std_logic_1164.std_logic (ieee std_logic_1164 std_logic)))
(_type (_external ~extieee.std_logic_1164.std_ulogic (ieee std_logic_1164 std_ulogic)))
)
(_model . tt 1 -1
)
)
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