📄 1dchufa.mgf

📁 d 触发器简单的d触发器
💻 MGF
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I 000044 55 675           1197370345687 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
  (_version v30)
  (_time 1197370345703 2007.12.11 18:52:25)
  (_source (\./src/dcf.vhd\))
  (_use (std(standard))(ieee(std_logic_1164)))
  (_entity
    (_time 1197370345640)
    (_use )
  )
  (_object
    (_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
    (_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
    (_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
    (_process
      (line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
    )
    (_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
  )
  (_model . dcf 1 -1
  )
)
I 000044 55 675           1197370348860 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
  (_version v30)
  (_time 1197370348859 2007.12.11 18:52:28)
  (_source (\./src/dcf.vhd\))
  (_use (std(standard))(ieee(std_logic_1164)))
  (_entity
    (_time 1197370345640)
    (_use )
  )
  (_object
    (_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
    (_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
    (_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
    (_process
      (line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
    )
    (_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
  )
  (_model . dcf 1 -1
  )
)
I 000044 55 675           1197371216218 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
  (_version v30)
  (_time 1197371216218 2007.12.11 19:06:56)
  (_source (\./src/dcf.vhd\))
  (_use (std(standard))(ieee(std_logic_1164)))
  (_entity
    (_time 1197370345640)
    (_use )
  )
  (_object
    (_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
    (_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
    (_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
    (_process
      (line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
    )
    (_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
  )
  (_model . dcf 1 -1
  )
)
I 000044 55 675           1197371234844 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
  (_version v30)
  (_time 1197371234843 2007.12.11 19:07:14)
  (_source (\./src/dcf.vhd\))
  (_use (std(standard))(ieee(std_logic_1164)))
  (_entity
    (_time 1197370345640)
    (_use )
  )
  (_object
    (_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
    (_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
    (_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
    (_process
      (line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
    )
    (_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
  )
  (_model . dcf 1 -1
  )
)
I 000044 55 675           1197371324297 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
  (_version v30)
  (_time 1197371324296 2007.12.11 19:08:44)
  (_source (\./src/dcf.vhd\))
  (_use (std(standard))(ieee(std_logic_1164)))
  (_entity
    (_time 1197370345640)
    (_use )
  )
  (_object
    (_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
    (_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
    (_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
    (_process
      (line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
    )
    (_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
  )
  (_model . dcf 1 -1
  )
)
I 000044 55 675           1197371335938 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
  (_version v30)
  (_time 1197371335937 2007.12.11 19:08:55)
  (_source (\./src/dcf.vhd\))
  (_use (std(standard))(ieee(std_logic_1164)))
  (_entity
    (_time 1197370345640)
    (_use )
  )
  (_object
    (_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
    (_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
    (_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
    (_process
      (line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
    )
    (_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
  )
  (_model . dcf 1 -1
  )
)
I 000044 55 675           1197371364188 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
  (_version v30)
  (_time 1197371364187 2007.12.11 19:09:24)
  (_source (\./src/dcf.vhd\))
  (_use (std(standard))(ieee(std_logic_1164)))
  (_entity
    (_time 1197370345640)
    (_use )
  )
  (_object
    (_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
    (_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
    (_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
    (_process
      (line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
    )
    (_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
  )
  (_model . dcf 1 -1
  )
)
I 000044 55 675           1197371369751 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
  (_version v30)
  (_time 1197371369750 2007.12.11 19:09:29)
  (_source (\./src/dcf.vhd\))
  (_use (std(standard))(ieee(std_logic_1164)))
  (_entity
    (_time 1197370345640)
    (_use )
  )
  (_object
    (_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
    (_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
    (_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
    (_process
      (line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
    )
    (_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
  )
  (_model . dcf 1 -1
  )
)
I 000044 55 675           1197371378485 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
  (_version v30)
  (_time 1197371378484 2007.12.11 19:09:38)
  (_source (\./src/dcf.vhd\))
  (_use (std(standard))(ieee(std_logic_1164)))
  (_entity
    (_time 1197370345640)
    (_use )
  )
  (_object
    (_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
    (_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
    (_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
    (_process
      (line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
    )
    (_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
  )
  (_model . dcf 1 -1
  )
)
I 000044 55 675           1197371414751 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
  (_version v30)
  (_time 1197371414750 2007.12.11 19:10:14)
  (_source (\./src/dcf.vhd\))
  (_use (std(standard))(ieee(std_logic_1164)))
  (_entity
    (_time 1197370345640)
    (_use )
  )
  (_object
    (_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
    (_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
    (_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
    (_process
      (line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
    )
    (_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
  )
  (_model . dcf 1 -1
  )
)
I 000044 55 675           1197371422563 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
  (_version v30)
  (_time 1197371422562 2007.12.11 19:10:22)
  (_source (\./src/dcf.vhd\))
  (_use (std(standard))(ieee(std_logic_1164)))
  (_entity
    (_time 1197370345640)
    (_use )
  )
  (_object
    (_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
    (_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
    (_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
    (_process
      (line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
    )
    (_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
  )
  (_model . dcf 1 -1
  )
)
I 000044 55 675           1197371542110 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
  (_version v30)
  (_time 1197371542109 2007.12.11 19:12:22)
  (_source (\./src/dcf.vhd\))
  (_use (std(standard))(ieee(std_logic_1164)))
  (_entity
    (_time 1197370345640)
    (_use )
  )
  (_object
    (_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
    (_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
    (_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
    (_process
      (line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
    )
    (_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
  )
  (_model . dcf 1 -1
  )
)
I 000044 55 675           1197371549079 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
  (_version v30)
  (_time 1197371549078 2007.12.11 19:12:29)
  (_source (\./src/dcf.vhd\))
  (_use (std(standard))(ieee(std_logic_1164)))
  (_entity
    (_time 1197370345640)
    (_use )
  )
  (_object
    (_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
    (_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
    (_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
    (_process
      (line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
    )
    (_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
  )
  (_model . dcf 1 -1
  )
)
I 000044 55 675           1197371601360 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
  (_version v30)
  (_time 1197371601359 2007.12.11 19:13:21)
  (_source (\./src/dcf.vhd\))
  (_use (std(standard))(ieee(std_logic_1164)))
  (_entity
    (_time 1197370345640)
    (_use )
  )
  (_object
    (_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
    (_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
    (_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
    (_process
      (line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
    )
    (_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
  )
  (_model . dcf 1 -1
  )
)
I 000044 55 675           1197371627438 dcf(_unit VHDL (dcf 0 30 (dcf 0 40 ))
  (_version v30)
  (_time 1197371627437 2007.12.11 19:13:47)
  (_source (\./src/dcf.vhd\))
  (_use (std(standard))(ieee(std_logic_1164)))
  (_entity
    (_time 1197370345640)
    (_use )
  )
  (_object
    (_port (_internal d ~extSTD.STANDARD.BIT 0 32 (_entity (_in ))))
    (_port (_internal clk ~extSTD.STANDARD.BIT 0 33 (_entity (_in ))))
    (_port (_internal q ~extSTD.STANDARD.BIT 0 34 (_entity (_out ))))
    (_process
      (line__42(_architecture 0 0 42 (_process (_simple)(_target(2))(_sensitivity(1)(0)))))
    )
    (_type (_external ~extSTD.STANDARD.BIT (std STANDARD BIT)))
  )
  (_model . dcf 1 -1
12 3 下一页
💿 文件大小 13 K
👤 上传用户 wylyyzjz
📂 所属分类 VHDL/FPGA/Verilog
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