console.log

d 触发器 简单的d触发器

# Compile Architecture "yyq" of Entity "yyq"
# Error: COMP96_0015: yyq.vhd : (49, 13): ';' expected.
# Compile failure 1 Errors 0 Warnings  Analysis time :  0.0 [s]
acom $DSN/src/dcf.vhd $DSN/src/yyq.vhd
# Compile...
# File: c:\My_Designs\d\dchufa\src\dcf.vhd
# Compile Entity "dcf"
# Entity `dcf' has been skipped - no difference detected.
# Compile Architecture "dcf" of Entity "dcf"
# File: c:\My_Designs\d\dchufa\src\yyq.vhd
# Compile Entity "yyq"
# Entity `yyq' has been skipped - no difference detected.
# Compile Architecture "yyq" of Entity "yyq"
# Error: COMP96_0015: yyq.vhd : (49, 13): ';' expected.
# Compile failure 1 Errors 0 Warnings  Analysis time :  0.1 [s]
acom $DSN/src/yyq.vhd
# Compile...
# File: c:\My_Designs\d\dchufa\src\yyq.vhd
# Compile Entity "yyq"
# Entity `yyq' has been skipped - no difference detected.
# Compile Architecture "yyq" of Entity "yyq"
# Error: COMP96_0015: yyq.vhd : (49, 1): ';' expected.
# Error: COMP96_0015: yyq.vhd : (49, 13): ';' expected.
# Compile failure 2 Errors 0 Warnings  Analysis time :  0.0 [s]
acom $DSN/src/dcf.vhd $DSN/src/yyq.vhd
# Compile...
# File: c:\My_Designs\d\dchufa\src\dcf.vhd
# Compile Entity "dcf"
# Entity `dcf' has been skipped - no difference detected.
# Compile Architecture "dcf" of Entity "dcf"
# File: c:\My_Designs\d\dchufa\src\yyq.vhd
# Compile Entity "yyq"
# Entity `yyq' has been skipped - no difference detected.
# Compile Architecture "yyq" of Entity "yyq"
# Error: COMP96_0015: yyq.vhd : (49, 13): ';' expected.
# Compile failure 1 Errors 0 Warnings  Analysis time :  0.0 [s]
acom $DSN/src/dcf.vhd $DSN/src/yyq.vhd
# Compile...
# File: c:\My_Designs\d\dchufa\src\dcf.vhd
# Compile Entity "dcf"
# Entity `dcf' has been skipped - no difference detected.
# Compile Architecture "dcf" of Entity "dcf"
# File: c:\My_Designs\d\dchufa\src\yyq.vhd
# Compile Entity "yyq"
# Entity `yyq' has been skipped - no difference detected.
# Compile Architecture "yyq" of Entity "yyq"
# Error: COMP96_0015: yyq.vhd : (49, 15): ';' expected.
# Compile failure 1 Errors 0 Warnings  Analysis time :  0.0 [s]
acom $DSN/src/yyq.vhd
# Compile...
# File: c:\My_Designs\d\dchufa\src\yyq.vhd
# Compile Entity "yyq"
# Entity `yyq' has been skipped - no difference detected.
# Compile Architecture "yyq" of Entity "yyq"
# Error: COMP96_0018: yyq.vhd : (49, 12): Identifier expected.
# Compile failure 1 Errors 0 Warnings  Analysis time :  0.0 [s]
acom $DSN/src/dcf.vhd $DSN/src/yyq.vhd
# Compile...
# File: c:\My_Designs\d\dchufa\src\dcf.vhd
# Compile Entity "dcf"
# Entity `dcf' has been skipped - no difference detected.
# Compile Architecture "dcf" of Entity "dcf"
# File: c:\My_Designs\d\dchufa\src\yyq.vhd
# Compile Entity "yyq"
# Entity `yyq' has been skipped - no difference detected.
# Compile Architecture "yyq" of Entity "yyq"
# Error: COMP96_0100: yyq.vhd : (53, 20): Actual parameter type in port map does not match the port formal type "d".
# Error: COMP96_0100: yyq.vhd : (53, 25): Actual parameter type in port map does not match the port formal type "clk".
# Error: COMP96_0100: yyq.vhd : (53, 29): Actual parameter type in port map does not match the port formal type "q".
# Error: COMP96_0100: yyq.vhd : (54, 20): Actual parameter type in port map does not match the port formal type "d".
# Error: COMP96_0100: yyq.vhd : (54, 25): Actual parameter type in port map does not match the port formal type "clk".
# Error: COMP96_0100: yyq.vhd : (54, 29): Actual parameter type in port map does not match the port formal type "q".
# Error: COMP96_0100: yyq.vhd : (55, 20): Actual parameter type in port map does not match the port formal type "d".
# Error: COMP96_0100: yyq.vhd : (55, 25): Actual parameter type in port map does not match the port formal type "clk".
# Error: COMP96_0100: yyq.vhd : (55, 29): Actual parameter type in port map does not match the port formal type "q".
# Error: COMP96_0100: yyq.vhd : (56, 20): Actual parameter type in port map does not match the port formal type "d".
# Error: COMP96_0100: yyq.vhd : (56, 25): Actual parameter type in port map does not match the port formal type "clk".
# Error: COMP96_0100: yyq.vhd : (56, 29): Actual parameter type in port map does not match the port formal type "q".
# Compile failure 12 Errors 0 Warnings  Analysis time :  0.0 [s]
open -vhdl {C:\My_Designs\d\dchufa\src\yyq.vhd}
open -vhdl {C:\My_Designs\d\dchufa\src\dcf.vhd}
acom $DSN/src/dcf.vhd $DSN/src/yyq.vhd $DSN/src/yy.vhd $DSN/src/tt.vhd
# Compile...
# File: c:\My_Designs\d\dchufa\src\dcf.vhd
# Compile Entity "dcf"
# Entity `dcf' has been skipped - no difference detected.
# Compile Architecture "dcf" of Entity "dcf"
# File: c:\My_Designs\d\dchufa\src\yyq.vhd
# Compile Entity "yyq"
# Entity `yyq' has been skipped - no difference detected.
# Compile Architecture "yyq" of Entity "yyq"
# Error: COMP96_0100: yyq.vhd : (53, 20): Actual parameter type in port map does not match the port formal type "d".
# Error: COMP96_0100: yyq.vhd : (53, 25): Actual parameter type in port map does not match the port formal type "clk".
# Error: COMP96_0100: yyq.vhd : (53, 29): Actual parameter type in port map does not match the port formal type "q".
# Error: COMP96_0100: yyq.vhd : (54, 20): Actual parameter type in port map does not match the port formal type "d".
# Error: COMP96_0100: yyq.vhd : (54, 25): Actual parameter type in port map does not match the port formal type "clk".
# Error: COMP96_0100: yyq.vhd : (54, 29): Actual parameter type in port map does not match the port formal type "q".
# Error: COMP96_0100: yyq.vhd : (55, 20): Actual parameter type in port map does not match the port formal type "d".
# Error: COMP96_0100: yyq.vhd : (55, 25): Actual parameter type in port map does not match the port formal type "clk".
# Error: COMP96_0100: yyq.vhd : (55, 29): Actual parameter type in port map does not match the port formal type "q".
# Error: COMP96_0100: yyq.vhd : (56, 20): Actual parameter type in port map does not match the port formal type "d".
# Error: COMP96_0100: yyq.vhd : (56, 25): Actual parameter type in port map does not match the port formal type "clk".
# Error: COMP96_0100: yyq.vhd : (56, 29): Actual parameter type in port map does not match the port formal type "q".
# File: c:\My_Designs\d\dchufa\src\yy.vhd
# Compile Entity "yy"
# Compile Architecture "yy" of Entity "yy"
# File: c:\My_Designs\d\dchufa\src\tt.vhd
# Compile Entity "tt"
# Compile Architecture "tt" of Entity "tt"
# Compile failure 12 Errors 0 Warnings  Analysis time :  0.2 [s]
acom $DSN/src/dcf.vhd $DSN/src/yyq.vhd $DSN/src/yy.vhd $DSN/src/tt.vhd
# Compile...
# File: c:\My_Designs\d\dchufa\src\dcf.vhd
# Compile Entity "dcf"
# Entity `dcf' has been skipped - no difference detected.
# Compile Architecture "dcf" of Entity "dcf"
# File: c:\My_Designs\d\dchufa\src\yyq.vhd
# Compile Entity "yyq"
# Entity `yyq' has been skipped - no difference detected.
# Compile Architecture "yyq" of Entity "yyq"
# Error: COMP96_0134: yyq.vhd : (53, 6): Cannot find component declaration.
# Error: COMP96_0134: yyq.vhd : (54, 6): Cannot find component declaration.
# Error: COMP96_0134: yyq.vhd : (55, 6): Cannot find component declaration.
# Error: COMP96_0134: yyq.vhd : (56, 6): Cannot find component declaration.
# File: c:\My_Designs\d\dchufa\src\yy.vhd
# Compile Entity "yy"
# Entity `yy' has been skipped - no difference detected.
# Compile Architecture "yy" of Entity "yy"
# File: c:\My_Designs\d\dchufa\src\tt.vhd
# Compile Entity "tt"
# Entity `tt' has been skipped - no difference detected.
# Compile Architecture "tt" of Entity "tt"
# Compile failure 4 Errors 0 Warnings  Analysis time :  0.1 [s]
acom $DSN/src/dcf.vhd $DSN/src/yyq.vhd $DSN/src/yy.vhd $DSN/src/tt.vhd
# Compile...
# File: c:\My_Designs\d\dchufa\src\dcf.vhd
# Compile Entity "dcf"
# Entity `dcf' has been skipped - no difference detected.
# Compile Architecture "dcf" of Entity "dcf"
# File: c:\My_Designs\d\dchufa\src\yyq.vhd
# Compile Entity "yyq"
# Entity `yyq' has been skipped - no difference detected.
# Compile Architecture "yyq" of Entity "yyq"
# Error: COMP96_0134: yyq.vhd : (53, 6): Cannot find component declaration.
# Error: COMP96_0134: yyq.vhd : (54, 6): Cannot find component declaration.
# Error: COMP96_0134: yyq.vhd : (55, 6): Cannot find component declaration.
# Error: COMP96_0134: yyq.vhd : (56, 6): Cannot find component declaration.
# File: c:\My_Designs\d\dchufa\src\yy.vhd
# Compile Entity "yy"
# Entity `yy' has been skipped - no difference detected.
# Compile Architecture "yy" of Entity "yy"
# File: c:\My_Designs\d\dchufa\src\tt.vhd
# Compile Entity "tt"
# Entity `tt' has been skipped - no difference detected.
# Compile Architecture "tt" of Entity "tt"
# Compile failure 4 Errors 0 Warnings  Analysis time :  0.2 [s]
acom $DSN/src/dcf.vhd $DSN/src/yyq.vhd $DSN/src/yy.vhd $DSN/src/tt.vhd
# Compile...
# File: c:\My_Designs\d\dchufa\src\dcf.vhd
# Compile Entity "dcf"
# Entity `dcf' has been skipped - no difference detected.
# Compile Architecture "dcf" of Entity "dcf"
# File: c:\My_Designs\d\dchufa\src\yyq.vhd
# Compile Entity "yyq"
# Entity `yyq' has been skipped - no difference detected.
# Compile Architecture "yyq" of Entity "yyq"
# File: c:\My_Designs\d\dchufa\src\yy.vhd
# Compile Entity "yy"
# Entity `yy' has been skipped - no difference detected.
# Compile Architecture "yy" of Entity "yy"
# File: c:\My_Designs\d\dchufa\src\tt.vhd
# Compile Entity "tt"
# Entity `tt' has been skipped - no difference detected.
# Compile Architecture "tt" of Entity "tt"
# Compile success 0 Errors 0 Warnings  Analysis time :  0.2 [s]
# Simulation has been stopped
# ELBREAD: Elaboration process.
# ELBREAD: Elaboration time 0.0 [s].
asim -advdataflow  -retry 3  yyq yyq
# ELBREAD: Elaboration process.
# ELBREAD: Elaboration time 0.0 [s].
# asim: Stack memory: 32MB
# asim: Retval memory: 32MB
# KERNEL: Main thread initiated.
# KERNEL: Kernel process initialization phase.
# KERNEL: Time resolution set to 1ps.
# ELAB2: Elaboration final pass...
# ELAB2: Create instances ...
# ELAB2: Create instances complete.
# ELAB2: Elaboration final pass complete - time: 0.0 [s].
# KERNEL: Kernel process initialization done.
# Allocation: Simulator allocated 1052 kB (elbread=1023 elab2=4 kernel=25 sdf=0)
# 19:30, 2007年12月11日
# Simulation has been initialized
# Selected Top-Level: yyq (yyq)
run @100ns
# KERNEL: stopped at time: 100 ns
run @200ns
# KERNEL: stopped at time: 200 ns
run @300ns
# KERNEL: stopped at time: 300 ns
endsim
# Simulation has been stopped
asim -advdataflow  -retry 3  yyq yyq
# ELBREAD: Elaboration process.
# ELBREAD: Elaboration time 0.0 [s].
# asim: Stack memory: 32MB
# asim: Retval memory: 32MB
# KERNEL: Main thread initiated.
# KERNEL: Kernel process initialization phase.
# KERNEL: Time resolution set to 1ps.
# ELAB2: Elaboration final pass...
# ELAB2: Create instances ...
# ELAB2: Create instances complete.
# ELAB2: Elaboration final pass complete - time: 0.0 [s].
# KERNEL: Kernel process initialization done.
# Allocation: Simulator allocated 1052 kB (elbread=1023 elab2=4 kernel=25 sdf=0)
# 19:32, 2007年12月11日
# Simulation has been initialized
# Selected Top-Level: yyq (yyq)
run @100ns
# KERNEL: stopped at time: 100 ns
run @200ns
# KERNEL: stopped at time: 200 ns
# Simulation has been stopped