i2c.vo

IIc总线的源代码（vhdl语言）

// atom is at LC_X95_Y54_N4
stratix_lcell \uC_CTRL|i~3230_I (
// Equation(s):
// \uC_CTRL|i~3230  = \uC_CTRL|i~3187  & !\addr_bus[22]~combout  & !\addr_bus[11]~combout  & \uC_CTRL|i~3218 

	.clk(),
	.dataa(\uC_CTRL|i~3187 ),
	.datab(\addr_bus[22]~combout ),
	.datac(\addr_bus[11]~combout ),
	.datad(\uC_CTRL|i~3218 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\uC_CTRL|i~3230 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \uC_CTRL|i~3230_I .operation_mode = "normal";
defparam \uC_CTRL|i~3230_I .synch_mode = "off";
defparam \uC_CTRL|i~3230_I .register_cascade_mode = "off";
defparam \uC_CTRL|i~3230_I .sum_lutc_input = "datac";
defparam \uC_CTRL|i~3230_I .lut_mask = "0200";
defparam \uC_CTRL|i~3230_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at Pin_P5
stratix_io \addr_bus[19]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\addr_bus[19]~combout ),
	.regout(),
	.ddioregout(),
	.padio(addr_bus[19]));
// synopsys translate_off
defparam \addr_bus[19]~I .operation_mode = "input";
defparam \addr_bus[19]~I .ddio_mode = "none";
defparam \addr_bus[19]~I .input_register_mode = "none";
defparam \addr_bus[19]~I .output_register_mode = "none";
defparam \addr_bus[19]~I .oe_register_mode = "none";
defparam \addr_bus[19]~I .input_async_reset = "none";
defparam \addr_bus[19]~I .output_async_reset = "none";
defparam \addr_bus[19]~I .oe_async_reset = "none";
defparam \addr_bus[19]~I .input_sync_reset = "none";
defparam \addr_bus[19]~I .output_sync_reset = "none";
defparam \addr_bus[19]~I .oe_sync_reset = "none";
defparam \addr_bus[19]~I .input_power_up = "low";
defparam \addr_bus[19]~I .output_power_up = "low";
defparam \addr_bus[19]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_L2
stratix_io \as~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\as~combout ),
	.regout(),
	.ddioregout(),
	.padio(as));
// synopsys translate_off
defparam \as~I .operation_mode = "input";
defparam \as~I .ddio_mode = "none";
defparam \as~I .input_register_mode = "none";
defparam \as~I .output_register_mode = "none";
defparam \as~I .oe_register_mode = "none";
defparam \as~I .input_async_reset = "none";
defparam \as~I .output_async_reset = "none";
defparam \as~I .oe_async_reset = "none";
defparam \as~I .input_sync_reset = "none";
defparam \as~I .output_sync_reset = "none";
defparam \as~I .oe_sync_reset = "none";
defparam \as~I .input_power_up = "low";
defparam \as~I .output_power_up = "low";
defparam \as~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_L7
stratix_io \addr_bus[18]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\addr_bus[18]~combout ),
	.regout(),
	.ddioregout(),
	.padio(addr_bus[18]));
// synopsys translate_off
defparam \addr_bus[18]~I .operation_mode = "input";
defparam \addr_bus[18]~I .ddio_mode = "none";
defparam \addr_bus[18]~I .input_register_mode = "none";
defparam \addr_bus[18]~I .output_register_mode = "none";
defparam \addr_bus[18]~I .oe_register_mode = "none";
defparam \addr_bus[18]~I .input_async_reset = "none";
defparam \addr_bus[18]~I .output_async_reset = "none";
defparam \addr_bus[18]~I .oe_async_reset = "none";
defparam \addr_bus[18]~I .input_sync_reset = "none";
defparam \addr_bus[18]~I .output_sync_reset = "none";
defparam \addr_bus[18]~I .oe_sync_reset = "none";
defparam \addr_bus[18]~I .input_power_up = "low";
defparam \addr_bus[18]~I .output_power_up = "low";
defparam \addr_bus[18]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_J4
stratix_io \addr_bus[14]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\addr_bus[14]~combout ),
	.regout(),
	.ddioregout(),
	.padio(addr_bus[14]));
// synopsys translate_off
defparam \addr_bus[14]~I .operation_mode = "input";
defparam \addr_bus[14]~I .ddio_mode = "none";
defparam \addr_bus[14]~I .input_register_mode = "none";
defparam \addr_bus[14]~I .output_register_mode = "none";
defparam \addr_bus[14]~I .oe_register_mode = "none";
defparam \addr_bus[14]~I .input_async_reset = "none";
defparam \addr_bus[14]~I .output_async_reset = "none";
defparam \addr_bus[14]~I .oe_async_reset = "none";
defparam \addr_bus[14]~I .input_sync_reset = "none";
defparam \addr_bus[14]~I .output_sync_reset = "none";
defparam \addr_bus[14]~I .oe_sync_reset = "none";
defparam \addr_bus[14]~I .input_power_up = "low";
defparam \addr_bus[14]~I .output_power_up = "low";
defparam \addr_bus[14]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_K3
stratix_io \addr_bus[13]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\addr_bus[13]~combout ),
	.regout(),
	.ddioregout(),
	.padio(addr_bus[13]));
// synopsys translate_off
defparam \addr_bus[13]~I .operation_mode = "input";
defparam \addr_bus[13]~I .ddio_mode = "none";
defparam \addr_bus[13]~I .input_register_mode = "none";
defparam \addr_bus[13]~I .output_register_mode = "none";
defparam \addr_bus[13]~I .oe_register_mode = "none";
defparam \addr_bus[13]~I .input_async_reset = "none";
defparam \addr_bus[13]~I .output_async_reset = "none";
defparam \addr_bus[13]~I .oe_async_reset = "none";
defparam \addr_bus[13]~I .input_sync_reset = "none";
defparam \addr_bus[13]~I .output_sync_reset = "none";
defparam \addr_bus[13]~I .oe_sync_reset = "none";
defparam \addr_bus[13]~I .input_power_up = "low";
defparam \addr_bus[13]~I .output_power_up = "low";
defparam \addr_bus[13]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_K4
stratix_io \addr_bus[10]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\addr_bus[10]~combout ),
	.regout(),
	.ddioregout(),
	.padio(addr_bus[10]));
// synopsys translate_off
defparam \addr_bus[10]~I .operation_mode = "input";
defparam \addr_bus[10]~I .ddio_mode = "none";
defparam \addr_bus[10]~I .input_register_mode = "none";
defparam \addr_bus[10]~I .output_register_mode = "none";
defparam \addr_bus[10]~I .oe_register_mode = "none";
defparam \addr_bus[10]~I .input_async_reset = "none";
defparam \addr_bus[10]~I .output_async_reset = "none";
defparam \addr_bus[10]~I .oe_async_reset = "none";
defparam \addr_bus[10]~I .input_sync_reset = "none";
defparam \addr_bus[10]~I .output_sync_reset = "none";
defparam \addr_bus[10]~I .oe_sync_reset = "none";
defparam \addr_bus[10]~I .input_power_up = "low";
defparam \addr_bus[10]~I .output_power_up = "low";
defparam \addr_bus[10]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at LC_X95_Y48_N2
stratix_lcell \uC_CTRL|i~3165_I (
// Equation(s):
// \uC_CTRL|i~3165  = !\addr_bus[18]~combout  & !\addr_bus[14]~combout  & !\addr_bus[13]~combout  & !\addr_bus[10]~combout 

	.clk(),
	.dataa(\addr_bus[18]~combout ),
	.datab(\addr_bus[14]~combout ),
	.datac(\addr_bus[13]~combout ),
	.datad(\addr_bus[10]~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\uC_CTRL|i~3165 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \uC_CTRL|i~3165_I .operation_mode = "normal";
defparam \uC_CTRL|i~3165_I .synch_mode = "off";
defparam \uC_CTRL|i~3165_I .register_cascade_mode = "off";
defparam \uC_CTRL|i~3165_I .sum_lutc_input = "datac";
defparam \uC_CTRL|i~3165_I .lut_mask = "0001";
defparam \uC_CTRL|i~3165_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at Pin_N3
stratix_io \addr_bus[9]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\addr_bus[9]~combout ),
	.regout(),
	.ddioregout(),
	.padio(addr_bus[9]));
// synopsys translate_off
defparam \addr_bus[9]~I .operation_mode = "input";
defparam \addr_bus[9]~I .ddio_mode = "none";
defparam \addr_bus[9]~I .input_register_mode = "none";
defparam \addr_bus[9]~I .output_register_mode = "none";
defparam \addr_bus[9]~I .oe_register_mode = "none";
defparam \addr_bus[9]~I .input_async_reset = "none";
defparam \addr_bus[9]~I .output_async_reset = "none";
defparam \addr_bus[9]~I .oe_async_reset = "none";
defparam \addr_bus[9]~I .input_sync_reset = "none";
defparam \addr_bus[9]~I .output_sync_reset = "none";
defparam \addr_bus[9]~I .oe_sync_reset = "none";
defparam \addr_bus[9]~I .input_power_up = "low";
defparam \addr_bus[9]~I .output_power_up = "low";
defparam \addr_bus[9]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_N2
stratix_io \addr_bus[17]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\addr_bus[17]~combout ),
	.regout(),
	.ddioregout(),
	.padio(addr_bus[17]));
// synopsys translate_off
defparam \addr_bus[17]~I .operation_mode = "input";
defparam \addr_bus[17]~I .ddio_mode = "none";
defparam \addr_bus[17]~I .input_register_mode = "none";
defparam \addr_bus[17]~I .output_register_mode = "none";
defparam \addr_bus[17]~I .oe_register_mode = "none";
defparam \addr_bus[17]~I .input_async_reset = "none";
defparam \addr_bus[17]~I .output_async_reset = "none";
defparam \addr_bus[17]~I .oe_async_reset = "none";
defparam \addr_bus[17]~I .input_sync_reset = "none";
defparam \addr_bus[17]~I .output_sync_reset = "none";
defparam \addr_bus[17]~I .oe_sync_reset = "none";
defparam \addr_bus[17]~I .input_power_up = "low";
defparam \addr_bus[17]~I .output_power_up = "low";
defparam \addr_bus[17]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at LC_X95_Y42_N3
stratix_lcell \uC_CTRL|i~3212_I (
// Equation(s):
// \uC_CTRL|i~3212  = !\addr_bus[9]~combout  & !\addr_bus[17]~combout 

	.clk(),
	.dataa(\addr_bus[9]~combout ),
	.datab(vcc),
	.datac(vcc),
	.datad(\addr_bus[17]~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\uC_CTRL|i~3212 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \uC_CTRL|i~3212_I .operation_mode = "normal";
defparam \uC_CTRL|i~3212_I .synch_mode = "off";
defparam \uC_CTRL|i~3212_I .register_cascade_mode = "off";
defparam \uC_CTRL|i~3212_I .sum_lutc_input = "datac";
defparam \uC_CTRL|i~3212_I .lut_mask = "0055";
defparam \uC_CTRL|i~3212_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at Pin_N4
stratix_io \ds~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\ds~combout ),
	.regout(),
	.ddioregout(),
	.padio(ds));
// synopsys translate_off
defparam \ds~I .operation_mode = "input";
defparam \ds~I .ddio_mode = "none";
defparam \ds~I .input_register_mode = "none";
defparam \ds~I .output_register_mode = "none";
defparam \ds~I .oe_register_mode = "none";
defparam \ds~I .input_async_reset = "none";
defparam \ds~I .output_async_reset = "none";
defparam \ds~I .oe_async_reset = "none";
defparam \ds~I .input_sync_reset = "none";
defparam \ds~I .output_sync_reset = "none";
defparam \ds~I .oe_sync_reset = "none";
defparam \ds~I .input_power_up = "low";
defparam \ds~I .output_power_up = "low";
defparam \ds~I .oe_power_up = "low";